ZZY
05c637e594
- 重命名和重构了多个文件，包括 lexer、parser 和 AST 相关代码 - 添加了日志功能，使用 LOG_* 宏替代原有的 error 和 warn 函数 - 优化了错误处理和内存分配方式 - 调整了代码结构，提高了模块化和可读性
548 lines
17 KiB
C
548 lines
17 KiB
C
// Copyright 2022 Charles Lohr, you may use this file or any portions herein under any of the BSD, MIT, or CC0 licenses.
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#ifndef _MINI_RV32IMAH_H
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#define _MINI_RV32IMAH_H
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/**
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To use mini-rv32ima.h for the bare minimum, the following:
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#define MINI_RV32_RAM_SIZE ram_amt
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#define MINIRV32_IMPLEMENTATION
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#include "mini-rv32ima.h"
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Though, that's not _that_ interesting. You probably want I/O!
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Notes:
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* There is a dedicated CLNT at 0x10000000.
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* There is free MMIO from there to 0x12000000.
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* You can put things like a UART, or whatever there.
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* Feel free to override any of the functionality with macros.
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*/
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#ifndef MINIRV32WARN
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#define MINIRV32WARN( x... );
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#endif
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#ifndef MINIRV32_DECORATE
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#define MINIRV32_DECORATE static
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#endif
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#ifndef MINIRV32_RAM_IMAGE_OFFSET
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#define MINIRV32_RAM_IMAGE_OFFSET 0x80000000
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#endif
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#ifndef MINIRV32_MMIO_RANGE
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#define MINIRV32_MMIO_RANGE(n) (0x10000000 <= (n) && (n) < 0x12000000)
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#endif
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#ifndef MINIRV32_POSTEXEC
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#define MINIRV32_POSTEXEC(...);
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#endif
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#ifndef MINIRV32_HANDLE_MEM_STORE_CONTROL
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#define MINIRV32_HANDLE_MEM_STORE_CONTROL(...);
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#endif
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#ifndef MINIRV32_HANDLE_MEM_LOAD_CONTROL
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#define MINIRV32_HANDLE_MEM_LOAD_CONTROL(...);
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#endif
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#ifndef MINIRV32_OTHERCSR_WRITE
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#define MINIRV32_OTHERCSR_WRITE(...);
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#endif
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#ifndef MINIRV32_OTHERCSR_READ
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#define MINIRV32_OTHERCSR_READ(...);
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#endif
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#ifndef MINIRV32_CUSTOM_MEMORY_BUS
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#define MINIRV32_STORE4( ofs, val ) *(uint32_t*)(image + ofs) = val
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#define MINIRV32_STORE2( ofs, val ) *(uint16_t*)(image + ofs) = val
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#define MINIRV32_STORE1( ofs, val ) *(uint8_t*)(image + ofs) = val
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#define MINIRV32_LOAD4( ofs ) *(uint32_t*)(image + ofs)
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#define MINIRV32_LOAD2( ofs ) *(uint16_t*)(image + ofs)
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#define MINIRV32_LOAD1( ofs ) *(uint8_t*)(image + ofs)
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#define MINIRV32_LOAD2_SIGNED( ofs ) *(int16_t*)(image + ofs)
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#define MINIRV32_LOAD1_SIGNED( ofs ) *(int8_t*)(image + ofs)
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#endif
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// As a note: We quouple-ify these, because in HLSL, we will be operating with
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// uint4's. We are going to uint4 data to/from system RAM.
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//
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// We're going to try to keep the full processor state to 12 x uint4.
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struct MiniRV32IMAState
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{
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uint32_t regs[32];
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uint32_t pc;
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uint32_t mstatus;
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uint32_t cyclel;
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uint32_t cycleh;
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uint32_t timerl;
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uint32_t timerh;
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uint32_t timermatchl;
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uint32_t timermatchh;
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uint32_t mscratch;
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uint32_t mtvec;
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uint32_t mie;
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uint32_t mip;
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uint32_t mepc;
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uint32_t mtval;
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uint32_t mcause;
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// Note: only a few bits are used. (Machine = 3, User = 0)
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// Bits 0..1 = privilege.
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// Bit 2 = WFI (Wait for interrupt)
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// Bit 3+ = Load/Store reservation LSBs.
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uint32_t extraflags;
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};
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#ifndef MINIRV32_STEPPROTO
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MINIRV32_DECORATE int32_t MiniRV32IMAStep( struct MiniRV32IMAState * state, uint8_t * image, uint32_t vProcAddress, uint32_t elapsedUs, int count );
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#endif
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#ifdef MINIRV32_IMPLEMENTATION
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#ifndef MINIRV32_CUSTOM_INTERNALS
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#define CSR( x ) state->x
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#define SETCSR( x, val ) { state->x = val; }
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#define REG( x ) state->regs[x]
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#define REGSET( x, val ) { state->regs[x] = val; }
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#endif
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#ifndef MINIRV32_STEPPROTO
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MINIRV32_DECORATE int32_t MiniRV32IMAStep( struct MiniRV32IMAState * state, uint8_t * image, uint32_t vProcAddress, uint32_t elapsedUs, int count )
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#else
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MINIRV32_STEPPROTO
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#endif
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{
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uint32_t new_timer = CSR( timerl ) + elapsedUs;
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if( new_timer < CSR( timerl ) ) CSR( timerh )++;
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CSR( timerl ) = new_timer;
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// Handle Timer interrupt.
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if( ( CSR( timerh ) > CSR( timermatchh ) || ( CSR( timerh ) == CSR( timermatchh ) && CSR( timerl ) > CSR( timermatchl ) ) ) && ( CSR( timermatchh ) || CSR( timermatchl ) ) )
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{
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CSR( extraflags ) &= ~4; // Clear WFI
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CSR( mip ) |= 1<<7; //MTIP of MIP // https://stackoverflow.com/a/61916199/2926815 Fire interrupt.
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}
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else
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CSR( mip ) &= ~(1<<7);
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// If WFI, don't run processor.
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if( CSR( extraflags ) & 4 )
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return 1;
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uint32_t trap = 0;
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uint32_t rval = 0;
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uint32_t pc = CSR( pc );
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uint32_t cycle = CSR( cyclel );
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if( ( CSR( mip ) & (1<<7) ) && ( CSR( mie ) & (1<<7) /*mtie*/ ) && ( CSR( mstatus ) & 0x8 /*mie*/) )
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{
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// Timer interrupt.
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trap = 0x80000007;
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pc -= 4;
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}
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else // No timer interrupt? Execute a bunch of instructions.
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for( int icount = 0; icount < count; icount++ )
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{
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uint32_t ir = 0;
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rval = 0;
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cycle++;
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uint32_t ofs_pc = pc - MINIRV32_RAM_IMAGE_OFFSET;
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if( ofs_pc >= MINI_RV32_RAM_SIZE )
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{
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trap = 1 + 1; // Handle access violation on instruction read.
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break;
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}
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else if( ofs_pc & 3 )
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{
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trap = 1 + 0; //Handle PC-misaligned access
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break;
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}
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else
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{
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ir = MINIRV32_LOAD4( ofs_pc );
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uint32_t rdid = (ir >> 7) & 0x1f;
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switch( ir & 0x7f )
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{
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case 0x37: // LUI (0b0110111)
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rval = ( ir & 0xfffff000 );
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break;
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case 0x17: // AUIPC (0b0010111)
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rval = pc + ( ir & 0xfffff000 );
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break;
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case 0x6F: // JAL (0b1101111)
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{
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int32_t reladdy = ((ir & 0x80000000)>>11) | ((ir & 0x7fe00000)>>20) | ((ir & 0x00100000)>>9) | ((ir&0x000ff000));
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if( reladdy & 0x00100000 ) reladdy |= 0xffe00000; // Sign extension.
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rval = pc + 4;
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pc = pc + reladdy - 4;
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break;
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}
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case 0x67: // JALR (0b1100111)
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{
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uint32_t imm = ir >> 20;
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int32_t imm_se = imm | (( imm & 0x800 )?0xfffff000:0);
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rval = pc + 4;
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pc = ( (REG( (ir >> 15) & 0x1f ) + imm_se) & ~1) - 4;
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break;
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}
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case 0x63: // Branch (0b1100011)
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{
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uint32_t immm4 = ((ir & 0xf00)>>7) | ((ir & 0x7e000000)>>20) | ((ir & 0x80) << 4) | ((ir >> 31)<<12);
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if( immm4 & 0x1000 ) immm4 |= 0xffffe000;
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int32_t rs1 = REG((ir >> 15) & 0x1f);
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int32_t rs2 = REG((ir >> 20) & 0x1f);
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immm4 = pc + immm4 - 4;
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rdid = 0;
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switch( ( ir >> 12 ) & 0x7 )
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{
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// BEQ, BNE, BLT, BGE, BLTU, BGEU
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case 0: if( rs1 == rs2 ) pc = immm4; break;
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case 1: if( rs1 != rs2 ) pc = immm4; break;
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case 4: if( rs1 < rs2 ) pc = immm4; break;
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case 5: if( rs1 >= rs2 ) pc = immm4; break; //BGE
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case 6: if( (uint32_t)rs1 < (uint32_t)rs2 ) pc = immm4; break; //BLTU
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case 7: if( (uint32_t)rs1 >= (uint32_t)rs2 ) pc = immm4; break; //BGEU
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default: trap = (2+1);
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}
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break;
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}
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case 0x03: // Load (0b0000011)
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{
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uint32_t rs1 = REG((ir >> 15) & 0x1f);
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uint32_t imm = ir >> 20;
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int32_t imm_se = imm | (( imm & 0x800 )?0xfffff000:0);
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uint32_t rsval = rs1 + imm_se;
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rsval -= MINIRV32_RAM_IMAGE_OFFSET;
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if( rsval >= MINI_RV32_RAM_SIZE-3 )
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{
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rsval += MINIRV32_RAM_IMAGE_OFFSET;
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if( MINIRV32_MMIO_RANGE( rsval ) ) // UART, CLNT
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{
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MINIRV32_HANDLE_MEM_LOAD_CONTROL( rsval, rval );
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}
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else
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{
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trap = (5+1);
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rval = rsval;
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}
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}
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else
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{
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switch( ( ir >> 12 ) & 0x7 )
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{
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//LB, LH, LW, LBU, LHU
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case 0: rval = MINIRV32_LOAD1_SIGNED( rsval ); break;
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case 1: rval = MINIRV32_LOAD2_SIGNED( rsval ); break;
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case 2: rval = MINIRV32_LOAD4( rsval ); break;
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case 4: rval = MINIRV32_LOAD1( rsval ); break;
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case 5: rval = MINIRV32_LOAD2( rsval ); break;
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default: trap = (2+1);
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}
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}
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break;
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}
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case 0x23: // Store 0b0100011
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{
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uint32_t rs1 = REG((ir >> 15) & 0x1f);
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uint32_t rs2 = REG((ir >> 20) & 0x1f);
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uint32_t addy = ( ( ir >> 7 ) & 0x1f ) | ( ( ir & 0xfe000000 ) >> 20 );
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if( addy & 0x800 ) addy |= 0xfffff000;
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addy += rs1 - MINIRV32_RAM_IMAGE_OFFSET;
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rdid = 0;
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if( addy >= MINI_RV32_RAM_SIZE-3 )
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{
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addy += MINIRV32_RAM_IMAGE_OFFSET;
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if( MINIRV32_MMIO_RANGE( addy ) )
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{
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MINIRV32_HANDLE_MEM_STORE_CONTROL( addy, rs2 );
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}
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else
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{
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trap = (7+1); // Store access fault.
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rval = addy;
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}
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}
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else
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{
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switch( ( ir >> 12 ) & 0x7 )
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{
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//SB, SH, SW
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case 0: MINIRV32_STORE1( addy, rs2 ); break;
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case 1: MINIRV32_STORE2( addy, rs2 ); break;
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case 2: MINIRV32_STORE4( addy, rs2 ); break;
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default: trap = (2+1);
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}
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}
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break;
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}
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case 0x13: // Op-immediate 0b0010011
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case 0x33: // Op 0b0110011
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{
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uint32_t imm = ir >> 20;
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imm = imm | (( imm & 0x800 )?0xfffff000:0);
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uint32_t rs1 = REG((ir >> 15) & 0x1f);
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uint32_t is_reg = !!( ir & 0x20 );
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uint32_t rs2 = is_reg ? REG(imm & 0x1f) : imm;
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if( is_reg && ( ir & 0x02000000 ) )
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{
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switch( (ir>>12)&7 ) //0x02000000 = RV32M
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{
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case 0: rval = rs1 * rs2; break; // MUL
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#ifndef CUSTOM_MULH // If compiling on a system that doesn't natively, or via libgcc support 64-bit math.
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case 1: rval = ((int64_t)((int32_t)rs1) * (int64_t)((int32_t)rs2)) >> 32; break; // MULH
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case 2: rval = ((int64_t)((int32_t)rs1) * (uint64_t)rs2) >> 32; break; // MULHSU
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case 3: rval = ((uint64_t)rs1 * (uint64_t)rs2) >> 32; break; // MULHU
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#else
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CUSTOM_MULH
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#endif
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case 4: if( rs2 == 0 ) rval = -1; else rval = ((int32_t)rs1 == INT32_MIN && (int32_t)rs2 == -1) ? rs1 : ((int32_t)rs1 / (int32_t)rs2); break; // DIV
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case 5: if( rs2 == 0 ) rval = 0xffffffff; else rval = rs1 / rs2; break; // DIVU
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case 6: if( rs2 == 0 ) rval = rs1; else rval = ((int32_t)rs1 == INT32_MIN && (int32_t)rs2 == -1) ? 0 : ((uint32_t)((int32_t)rs1 % (int32_t)rs2)); break; // REM
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case 7: if( rs2 == 0 ) rval = rs1; else rval = rs1 % rs2; break; // REMU
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}
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}
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else
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{
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switch( (ir>>12)&7 ) // These could be either op-immediate or op commands. Be careful.
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{
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case 0: rval = (is_reg && (ir & 0x40000000) ) ? ( rs1 - rs2 ) : ( rs1 + rs2 ); break;
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case 1: rval = rs1 << (rs2 & 0x1F); break;
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case 2: rval = (int32_t)rs1 < (int32_t)rs2; break;
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case 3: rval = rs1 < rs2; break;
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case 4: rval = rs1 ^ rs2; break;
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case 5: rval = (ir & 0x40000000 ) ? ( ((int32_t)rs1) >> (rs2 & 0x1F) ) : ( rs1 >> (rs2 & 0x1F) ); break;
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case 6: rval = rs1 | rs2; break;
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case 7: rval = rs1 & rs2; break;
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}
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}
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break;
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}
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case 0x0f: // 0b0001111
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rdid = 0; // fencetype = (ir >> 12) & 0b111; We ignore fences in this impl.
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break;
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case 0x73: // Zifencei+Zicsr (0b1110011)
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{
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uint32_t csrno = ir >> 20;
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uint32_t microop = ( ir >> 12 ) & 0x7;
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if( (microop & 3) ) // It's a Zicsr function.
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{
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int rs1imm = (ir >> 15) & 0x1f;
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uint32_t rs1 = REG(rs1imm);
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uint32_t writeval = rs1;
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// https://raw.githubusercontent.com/riscv/virtual-memory/main/specs/663-Svpbmt.pdf
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// Generally, support for Zicsr
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switch( csrno )
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{
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case 0x340: rval = CSR( mscratch ); break;
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case 0x305: rval = CSR( mtvec ); break;
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case 0x304: rval = CSR( mie ); break;
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case 0xC00: rval = cycle; break;
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case 0x344: rval = CSR( mip ); break;
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case 0x341: rval = CSR( mepc ); break;
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case 0x300: rval = CSR( mstatus ); break; //mstatus
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case 0x342: rval = CSR( mcause ); break;
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case 0x343: rval = CSR( mtval ); break;
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case 0xf11: rval = 0xff0ff0ff; break; //mvendorid
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case 0x301: rval = 0x40401101; break; //misa (XLEN=32, IMA+X)
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//case 0x3B0: rval = 0; break; //pmpaddr0
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//case 0x3a0: rval = 0; break; //pmpcfg0
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//case 0xf12: rval = 0x00000000; break; //marchid
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//case 0xf13: rval = 0x00000000; break; //mimpid
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//case 0xf14: rval = 0x00000000; break; //mhartid
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default:
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MINIRV32_OTHERCSR_READ( csrno, rval );
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break;
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}
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switch( microop )
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{
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case 1: writeval = rs1; break; //CSRRW
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case 2: writeval = rval | rs1; break; //CSRRS
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case 3: writeval = rval & ~rs1; break; //CSRRC
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case 5: writeval = rs1imm; break; //CSRRWI
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case 6: writeval = rval | rs1imm; break; //CSRRSI
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case 7: writeval = rval & ~rs1imm; break; //CSRRCI
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}
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switch( csrno )
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{
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case 0x340: SETCSR( mscratch, writeval ); break;
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case 0x305: SETCSR( mtvec, writeval ); break;
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case 0x304: SETCSR( mie, writeval ); break;
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case 0x344: SETCSR( mip, writeval ); break;
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case 0x341: SETCSR( mepc, writeval ); break;
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case 0x300: SETCSR( mstatus, writeval ); break; //mstatus
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case 0x342: SETCSR( mcause, writeval ); break;
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case 0x343: SETCSR( mtval, writeval ); break;
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//case 0x3a0: break; //pmpcfg0
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//case 0x3B0: break; //pmpaddr0
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//case 0xf11: break; //mvendorid
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//case 0xf12: break; //marchid
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//case 0xf13: break; //mimpid
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//case 0xf14: break; //mhartid
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//case 0x301: break; //misa
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default:
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MINIRV32_OTHERCSR_WRITE( csrno, writeval );
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break;
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}
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}
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else if( microop == 0x0 ) // "SYSTEM" 0b000
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{
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rdid = 0;
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if( ( ( csrno & 0xff ) == 0x02 ) ) // MRET
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{
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//https://raw.githubusercontent.com/riscv/virtual-memory/main/specs/663-Svpbmt.pdf
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//Table 7.6. MRET then in mstatus/mstatush sets MPV=0, MPP=0, MIE=MPIE, and MPIE=1. La
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// Should also update mstatus to reflect correct mode.
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uint32_t startmstatus = CSR( mstatus );
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uint32_t startextraflags = CSR( extraflags );
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SETCSR( mstatus , (( startmstatus & 0x80) >> 4) | ((startextraflags&3) << 11) | 0x80 );
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SETCSR( extraflags, (startextraflags & ~3) | ((startmstatus >> 11) & 3) );
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pc = CSR( mepc ) -4;
|
|
} else {
|
|
switch (csrno) {
|
|
case 0:
|
|
#ifndef ECALL_HANDLER
|
|
trap = ( CSR( extraflags ) & 3) ? (11+1) : (8+1); // ECALL; 8 = "Environment call from U-mode"; 11 = "Environment call from M-mode"
|
|
#else
|
|
ECALL_HANDLER(state);
|
|
trap = 0;
|
|
#endif
|
|
break;
|
|
case 1:
|
|
trap = (3+1); break; // EBREAK 3 = "Breakpoint"
|
|
case 0x105: //WFI (Wait for interrupts)
|
|
CSR( mstatus ) |= 8; //Enable interrupts
|
|
CSR( extraflags ) |= 4; //Infor environment we want to go to sleep.
|
|
SETCSR( pc, pc + 4 );
|
|
return 1;
|
|
default:
|
|
trap = (2+1); break; // Illegal opcode.
|
|
}
|
|
}
|
|
}
|
|
else
|
|
trap = (2+1); // Note micrrop 0b100 == undefined.
|
|
break;
|
|
}
|
|
case 0x2f: // RV32A (0b00101111)
|
|
{
|
|
uint32_t rs1 = REG((ir >> 15) & 0x1f);
|
|
uint32_t rs2 = REG((ir >> 20) & 0x1f);
|
|
uint32_t irmid = ( ir>>27 ) & 0x1f;
|
|
|
|
rs1 -= MINIRV32_RAM_IMAGE_OFFSET;
|
|
|
|
// We don't implement load/store from UART or CLNT with RV32A here.
|
|
|
|
if( rs1 >= MINI_RV32_RAM_SIZE-3 )
|
|
{
|
|
trap = (7+1); //Store/AMO access fault
|
|
rval = rs1 + MINIRV32_RAM_IMAGE_OFFSET;
|
|
}
|
|
else
|
|
{
|
|
rval = MINIRV32_LOAD4( rs1 );
|
|
|
|
// Referenced a little bit of https://github.com/franzflasch/riscv_em/blob/master/src/core/core.c
|
|
uint32_t dowrite = 1;
|
|
switch( irmid )
|
|
{
|
|
case 2: //LR.W (0b00010)
|
|
dowrite = 0;
|
|
CSR( extraflags ) = (CSR( extraflags ) & 0x07) | (rs1<<3);
|
|
break;
|
|
case 3: //SC.W (0b00011) (Make sure we have a slot, and, it's valid)
|
|
rval = ( CSR( extraflags ) >> 3 != ( rs1 & 0x1fffffff ) ); // Validate that our reservation slot is OK.
|
|
dowrite = !rval; // Only write if slot is valid.
|
|
break;
|
|
case 1: break; //AMOSWAP.W (0b00001)
|
|
case 0: rs2 += rval; break; //AMOADD.W (0b00000)
|
|
case 4: rs2 ^= rval; break; //AMOXOR.W (0b00100)
|
|
case 12: rs2 &= rval; break; //AMOAND.W (0b01100)
|
|
case 8: rs2 |= rval; break; //AMOOR.W (0b01000)
|
|
case 16: rs2 = ((int32_t)rs2<(int32_t)rval)?rs2:rval; break; //AMOMIN.W (0b10000)
|
|
case 20: rs2 = ((int32_t)rs2>(int32_t)rval)?rs2:rval; break; //AMOMAX.W (0b10100)
|
|
case 24: rs2 = (rs2<rval)?rs2:rval; break; //AMOMINU.W (0b11000)
|
|
case 28: rs2 = (rs2>rval)?rs2:rval; break; //AMOMAXU.W (0b11100)
|
|
default: trap = (2+1); dowrite = 0; break; //Not supported.
|
|
}
|
|
if( dowrite ) MINIRV32_STORE4( rs1, rs2 );
|
|
}
|
|
break;
|
|
}
|
|
default: trap = (2+1); // Fault: Invalid opcode.
|
|
}
|
|
|
|
// If there was a trap, do NOT allow register writeback.
|
|
if( trap ) {
|
|
SETCSR( pc, pc );
|
|
MINIRV32_POSTEXEC( pc, ir, trap );
|
|
break;
|
|
}
|
|
|
|
if( rdid )
|
|
{
|
|
REGSET( rdid, rval ); // Write back register.
|
|
}
|
|
}
|
|
|
|
MINIRV32_POSTEXEC( pc, ir, trap );
|
|
|
|
pc += 4;
|
|
}
|
|
|
|
// Handle traps and interrupts.
|
|
if( trap )
|
|
{
|
|
if( trap & 0x80000000 ) // If prefixed with 1 in MSB, it's an interrupt, not a trap.
|
|
{
|
|
SETCSR( mcause, trap );
|
|
SETCSR( mtval, 0 );
|
|
pc += 4; // PC needs to point to where the PC will return to.
|
|
}
|
|
else
|
|
{
|
|
SETCSR( mcause, trap - 1 );
|
|
SETCSR( mtval, (trap > 5 && trap <= 8)? rval : pc );
|
|
}
|
|
SETCSR( mepc, pc ); //TRICKY: The kernel advances mepc automatically.
|
|
//CSR( mstatus ) & 8 = MIE, & 0x80 = MPIE
|
|
// On an interrupt, the system moves current MIE into MPIE
|
|
SETCSR( mstatus, (( CSR( mstatus ) & 0x08) << 4) | (( CSR( extraflags ) & 3 ) << 11) );
|
|
pc = (CSR( mtvec ) - 4);
|
|
|
|
// If trapping, always enter machine mode.
|
|
CSR( extraflags ) |= 3;
|
|
|
|
trap = 0;
|
|
pc += 4;
|
|
}
|
|
|
|
if( CSR( cyclel ) > cycle ) CSR( cycleh )++;
|
|
SETCSR( cyclel, cycle );
|
|
SETCSR( pc, pc );
|
|
return 0;
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|