342 lines
13 KiB
C
342 lines
13 KiB
C
#ifndef __RV32I_GEN_H__
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#define __RV32I_GEN_H__
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/**
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31 25 24 20 19 15 14 12 11 7 6 0
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imm[31:12] rd 0110111 U lui
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imm[31:12] rd 0010111 U auipc
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imm[20|10:1|11|19:12] rd 1101111 J jal
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imm[11:0] rs1 000 rd 1100111 I jalr
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imm[12|10:5] rs2 rs1 000 imm[4:1|11] 1100011 B beq
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imm[12|10:5] rs2 rs1 001 imm[4:1|11] 1100011 B bne
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imm[12|10:5] rs2 rs1 100 imm[4:1|11] 1100011 B blt
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imm[12|10:5] rs2 rs1 101 imm[4:1|11] 1100011 B bge
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imm[12|10:5] rs2 rs1 110 imm[4:1|11] 1100011 B bltu
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imm[12|10:5] rs2 rs1 111 imm[4:1|11] 1100011 B bgeu
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imm[11:0] rs1 000 rd 0000011 I lb
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imm[11:0] rs1 001 rd 0000011 I lh
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imm[11:0] rs1 010 rd 0000011 I lw
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imm[11:0] rs1 100 rd 0000011 I lbu
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imm[11:0] rs1 101 rd 0000011 I lhu
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imm[11:5] rs2 rs1 000 imm[4:0] 0100011 S sb
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imm[11:5] rs2 rs1 001 imm[4:0] 0100011 S sh
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imm[11:5] rs2 rs1 010 imm[4:0] 0100011 S sw
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imm[11:0] rs1 000 rd 0010011 I addi
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imm[11:0] rs1 010 rd 0010011 I slti
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imm[11:0] rs1 011 rd 0010011 I sltiu
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imm[11:0] rs1 100 rd 0010011 I xori
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imm[11:0] rs1 110 rd 0010011 I ori
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imm[11:0] rs1 111 rd 0010011 I andi
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0000000 shamt rs1 001 rd 0010011 I slli
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0000000 shamt rs1 101 rd 0010011 I srli
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0100000 shamt rs1 101 rd 0010011 I srai
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0000000 rs2 rs1 000 rd 0110011 R add
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0100000 rs2 rs1 000 rd 0110011 R sub
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0000000 rs2 rs1 001 rd 0110011 R sll
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0000000 rs2 rs1 010 rd 0110011 R slt
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0000000 rs2 rs1 011 rd 0110011 R sltu
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0000000 rs2 rs1 100 rd 0110011 R xor
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0000000 rs2 rs1 101 rd 0110011 R srl
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0100000 rs2 rs1 101 rd 0110011 R sra
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0000000 rs2 rs1 110 rd 0110011 R or
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0000000 rs2 rs1 111 rd 0110011 R and
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0000 pred succ 00000 000 00000 0001111 I fence
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0000 0000 0000 00000 001 00000 0001111 I fence.i
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000000000000 00000 00 00000 1110011 I ecall
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000000000000 00000 000 00000 1110011 I ebreak
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csr rs1 001 rd 1110011 I csrrw
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csr rs1 010 rd 1110011 I csrrs
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csr rs1 011 rd 1110011 I csrrc
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csr zimm 101 rd 1110011 I csrrwi
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csr zimm 110 rd 1110011 I cssrrsi
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csr zimm 111 rd 1110011 I csrrci
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*/
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#include <stdint.h>
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// 寄存器枚举定义
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typedef enum {
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REG_X0, REG_X1, REG_X2, REG_X3, REG_X4, REG_X5, REG_X6, REG_X7,
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REG_X8, REG_X9, REG_X10, REG_X11, REG_X12, REG_X13, REG_X14, REG_X15,
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REG_X16, REG_X17, REG_X18, REG_X19, REG_X20, REG_X21, REG_X22, REG_X23,
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REG_X24, REG_X25, REG_X26, REG_X27, REG_X28, REG_X29, REG_X30, REG_X31,
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REG_ZERO = REG_X0, REG_RA = REG_X1, REG_SP = REG_X2, REG_GP = REG_X3,
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REG_TP = REG_X4, REG_T0 = REG_X5, REG_T1 = REG_X6, REG_T2 = REG_X7,
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REG_S0 = REG_X8, REG_S1 = REG_X9, REG_A0 = REG_X10, REG_A1 = REG_X11,
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REG_A2 = REG_X12, REG_A3 = REG_X13, REG_A4 = REG_X14, REG_A5 = REG_X15,
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REG_A6 = REG_X16, REG_A7 = REG_X17, REG_S2 = REG_X18, REG_S3 = REG_X19,
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REG_S4 = REG_X20, REG_S5 = REG_X21, REG_S6 = REG_X22, REG_S7 = REG_X23,
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REG_S8 = REG_X24, REG_S9 = REG_X25, REG_S10 = REG_X26, REG_S11 = REG_X27,
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REG_T3 = REG_X28, REG_T4 = REG_X29, REG_T5 = REG_X30, REG_T6 = REG_X31,
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} RV32Reg;
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/******************** 立即数处理宏 ********************/
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#define IMM_12BITS(imm) ((imm) & 0xFFF)
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#define IMM_20BITS(imm) ((imm) & 0xFFFFF)
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#define SHAMT_VAL(imm) ((imm) & 0x1F)
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#define CSR_VAL(csr) ((csr) & 0xFFF)
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// B型立即数编码（[12|10:5|4:1|11]）
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#define ENCODE_B_IMM(imm) ( \
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(((imm) >> 12) & 0x1) << 31 | /* imm[12:12] -> instr[31:31] */ \
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(((imm) >> 5) & 0x3F) << 25 | /* imm[10:5] -> instr[30:25] */ \
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(((imm) >> 1) & 0xF) << 8 | /* imm[4:1] -> instr[11:8] */ \
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(((imm) >> 11) & 0x1) << 7) /* imm[11:11] -> instr[7:7] */
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// J型立即数编码（[20|10:1|11|19:12]）W
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#define ENCODE_J_IMM(imm) ( \
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(((imm) >> 20) & 0x1) << 31 | /* imm[20:20] -> instr[31:31] */ \
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(((imm) >> 1) & 0x3FF)<< 21 | /* imm[10:1] -> instr[30:21] */ \
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(((imm) >> 11) & 0x1) << 20 | /* imm[11:11] -> instr[20:20] */ \
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(((imm) >> 12) & 0xFF) << 12) /* imm[19:12] -> instr[19:12] */
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/******************** 指令生成宏 ********************/
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// R型指令宏
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#define RV32_RTYPE(op, f3, f7, rd, rs1, rs2) (uint32_t)( \
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(0x33 | ((rd) << 7) | ((f3) << 12) | ((rs1) << 15) | \
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((rs2) << 20) | ((f7) << 25)) )
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// I型指令宏
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#define RV32_ITYPE(op, f3, rd, rs1, imm) (uint32_t)( \
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(op | ((rd) << 7) | ((f3) << 12) | ((rs1) << 15) | \
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(IMM_12BITS(imm) << 20)) )
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// S型指令宏
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#define RV32_STYPE(op, f3, rs1, rs2, imm) (uint32_t)( \
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(op | ((IMM_12BITS(imm) & 0xFE0) << 20) | ((rs1) << 15) | \
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((rs2) << 20) | ((f3) << 12) | ((IMM_12BITS(imm) & 0x1F) << 7)) )
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// B型指令宏
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#define RV32_BTYPE(op, f3, rs1, rs2, imm) (uint32_t)( \
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(op | (ENCODE_B_IMM(imm)) | ((rs1) << 15) | \
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((rs2) << 20) | ((f3) << 12)) )
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// U型指令宏
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#define RV32_UTYPE(op, rd, imm) (uint32_t)( \
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(op | ((rd) << 7) | (IMM_20BITS((imm) >> 12) << 12)) )
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// J型指令宏
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#define RV32_JTYPE(op, rd, imm) (uint32_t)( \
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(op | ((rd) << 7) | ENCODE_J_IMM(imm)) )
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/******************** U-type ********************/
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#define LUI(rd, imm) RV32_UTYPE(0x37, rd, imm)
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#define AUIPC(rd, imm) RV32_UTYPE(0x17, rd, imm)
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/******************** J-type ********************/
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#define JAL(rd, imm) RV32_JTYPE(0x6F, rd, imm)
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/******************** I-type ********************/
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#define JALR(rd, rs1, imm) RV32_ITYPE(0x67, 0x0, rd, rs1, imm)
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// Load instructions
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#define LB(rd, rs1, imm) RV32_ITYPE(0x03, 0x0, rd, rs1, imm)
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#define LH(rd, rs1, imm) RV32_ITYPE(0x03, 0x1, rd, rs1, imm)
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#define LW(rd, rs1, imm) RV32_ITYPE(0x03, 0x2, rd, rs1, imm)
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#define LBU(rd, rs1, imm) RV32_ITYPE(0x03, 0x4, rd, rs1, imm)
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#define LHU(rd, rs1, imm) RV32_ITYPE(0x03, 0x5, rd, rs1, imm)
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// Immediate arithmetic
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#define ADDI(rd, rs1, imm) RV32_ITYPE(0x13, 0x0, rd, rs1, imm)
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#define SLTI(rd, rs1, imm) RV32_ITYPE(0x13, 0x2, rd, rs1, imm)
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#define SLTIU(rd, rs1, imm) RV32_ITYPE(0x13, 0x3, rd, rs1, imm)
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#define XORI(rd, rs1, imm) RV32_ITYPE(0x13, 0x4, rd, rs1, imm)
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#define ORI(rd, rs1, imm) RV32_ITYPE(0x13, 0x6, rd, rs1, imm)
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#define ANDI(rd, rs1, imm) RV32_ITYPE(0x13, 0x7, rd, rs1, imm)
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// Shift instructions
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#define SLLI(rd, rs1, shamt) RV32_ITYPE(0x13, 0x1, rd, rs1, (0x00000000 | (shamt << 20)))
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#define SRLI(rd, rs1, shamt) RV32_ITYPE(0x13, 0x5, rd, rs1, (0x00000000 | (shamt << 20)))
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#define SRAI(rd, rs1, shamt) RV32_ITYPE(0x13, 0x5, rd, rs1, (0x40000000 | (shamt << 20)))
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/******************** B-type ********************/
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#define BEQ(rs1, rs2, imm) RV32_BTYPE(0x63, 0x0, rs1, rs2, imm)
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#define BNE(rs1, rs2, imm) RV32_BTYPE(0x63, 0x1, rs1, rs2, imm)
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#define BLT(rs1, rs2, imm) RV32_BTYPE(0x63, 0x4, rs1, rs2, imm)
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#define BGE(rs1, rs2, imm) RV32_BTYPE(0x63, 0x5, rs1, rs2, imm)
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#define BLTU(rs1, rs2, imm) RV32_BTYPE(0x63, 0x6, rs1, rs2, imm)
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#define BGEU(rs1, rs2, imm) RV32_BTYPE(0x63, 0x7, rs1, rs2, imm)
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/******************** S-type ********************/
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#define SB(rs2, rs1, imm) RV32_STYPE(0x23, 0x0, rs1, rs2, imm)
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#define SH(rs2, rs1, imm) RV32_STYPE(0x23, 0x1, rs1, rs2, imm)
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#define SW(rs2, rs1, imm) RV32_STYPE(0x23, 0x2, rs1, rs2, imm)
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/******************** R-type ********************/
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#define ADD(rd, rs1, rs2) RV32_RTYPE(0x33, 0x0, 0x00, rd, rs1, rs2)
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#define SUB(rd, rs1, rs2) RV32_RTYPE(0x33, 0x0, 0x20, rd, rs1, rs2)
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#define SLL(rd, rs1, rs2) RV32_RTYPE(0x33, 0x1, 0x00, rd, rs1, rs2)
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#define SLT(rd, rs1, rs2) RV32_RTYPE(0x33, 0x2, 0x00, rd, rs1, rs2)
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#define SLTU(rd, rs1, rs2) RV32_RTYPE(0x33, 0x3, 0x00, rd, rs1, rs2)
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#define XOR(rd, rs1, rs2) RV32_RTYPE(0x33, 0x4, 0x00, rd, rs1, rs2)
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#define SRL(rd, rs1, rs2) RV32_RTYPE(0x33, 0x5, 0x00, rd, rs1, rs2)
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#define SRA(rd, rs1, rs2) RV32_RTYPE(0x33, 0x5, 0x20, rd, rs1, rs2)
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#define OR(rd, rs1, rs2) RV32_RTYPE(0x33, 0x6, 0x00, rd, rs1, rs2)
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#define AND(rd, rs1, rs2) RV32_RTYPE(0x33, 0x7, 0x00, rd, rs1, rs2)
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/******************** I-type (system) ********************/
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#define FENCE(pred, succ) (uint32_t)( 0x0F | ((pred) << 23) | ((succ) << 27) )
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#define FENCE_I() (uint32_t)( 0x100F )
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#define ECALL() (uint32_t)( 0x73 )
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#define EBREAK() (uint32_t)( 0x100073 )
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// CSR instructions
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#define CSRRW(rd, csr, rs) RV32_ITYPE(0x73, 0x1, rd, rs, CSR_VAL(csr))
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#define CSRRS(rd, csr, rs) RV32_ITYPE(0x73, 0x2, rd, rs, CSR_VAL(csr))
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#define CSRRC(rd, csr, rs) RV32_ITYPE(0x73, 0x3, rd, rs, CSR_VAL(csr))
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#define CSRRWI(rd, csr, zimm) RV32_ITYPE(0x73, 0x5, rd, 0, (CSR_VAL(csr) | ((zimm) << 15)))
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#define CSRRSI(rd, csr, zimm) RV32_ITYPE(0x73, 0x6, rd, 0, (CSR_VAL(csr) | ((zimm) << 15)))
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#define CSRRCI(rd, csr, zimm) RV32_ITYPE(0x73, 0x7, rd, 0, (CSR_VAL(csr) | ((zimm) << 15)))
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/* M-Extention */
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#define MUL(rd, rs1, rs2) RV32_RTYPE(0x33, 0x0, 0x01, rd, rs1, rs2)
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#define DIV(rd, rs1, rs2) RV32_RTYPE(0x33, 0x0, 0x05, rd, rs1, rs2)
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#define REM(rd, rs1, rs2) RV32_RTYPE(0x33, 0x0, 0x07, rd, rs1, rs2)
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/******************** Pseudo-instructions ********************/
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// 伪指令
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// nop (No operation)
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#define NOP() ADDI(REG_X0, REG_X0, 0) // 无操作
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// neg rd, rs (Two's complement of rs)
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#define NEG(rd, rs) SUB(rd, REG_ZERO, rs) // 补码
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// negw rd, rs (Two's complement word of rs)
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#define NEGW(rd, rs) SUBW(rd, REG_ZERO, rs) // 字的补码
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// snez rd, rs (Set if ≠ zero)
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#define SNEZ(rd, rs) SLTU(rd, REG_X0, rs) // 非0则置位
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// sltz rd, rs (Set if < zero)
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#define SLTZ(rd, rs) SLT(rd, rs, REG_X0) // 小于0则置位
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// sgtz rd, rs (Set if > zero)
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#define SGTZ(rd, rs) SLT(rd, REG_X0, rs) // 大于0则置位
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// beqz rs, offset (Branch if = zero)
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#define BEQZ(rs, offset) BEQ(rs, REG_X0, offset) // 为0则转移
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// bnez rs, offset (Branch if ≠ zero)
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#define BNEZ(rs, offset) BNE(rs, REG_X0, offset) // 非0则转移
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// blez rs, offset (Branch if ≤ zero)
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#define BLEZ(rs, offset) BGE(REG_X0, rs, offset) // 小于等于0则转移
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// bgez rs, offset (Branch if ≥ zero)
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#define BGEZ(rs, offset) BGE(rs, REG_X0, offset) // 大于等于0则转移
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// bltz rs, offset (Branch if < zero)
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#define BLTZ(rs, offset) BLT(rs, REG_X0, offset) // 小于0则转移
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// bgtz rs, offset (Branch if > zero)
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#define BGTZ(rs, offset) BLT(REG_X0, rs, offset) // 大于0则转移
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// j offset (Jump)
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#define J(offset) JAL(REG_X0, offset) // 跳转
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// jr rs (Jump register)
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#define JR(rs) JALR(REG_X0, rs, 0) // 寄存器跳转
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// ret (Return from subroutine)
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#define RET() JALR(REG_X0, REG_RA, 0) // 从子过程返回
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// tail offset (Tail call far-away subroutine)
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#define TAIL_2(offset) AUIPC(REG_X6, offset), JAL(REG_X0, REG_X6, offset) // 尾调用远程子过程, 有2条指令
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#define TAIL(offset) TAIL_2(offset) // Warning this have 2 instructions
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// csrr csr, rd (Read CSR)
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#define CSRR(csr, rd) CSRRS(rd, csr, REG_X0) // 读CSR寄存器
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// csrw csr, rs (Write CSR)
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#define CSR W(csr, rs) CSRRW(csr, REG_X0, rs) // 写CSR寄存器
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// csrs csr, rs (Set bits in CSR)
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#define CSRS(csr, rs) CSRRS(REG_X0, csr, rs) // CSR寄存器置零位
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// csrrc csr, rs (Clear bits in CSR)
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#define CSRC(csr, rs) CSRRC(REG_X0, csr, rs) // CSR寄存器清
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// csrci csr, imm (Immediate clear bits in CSR)
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#define CSRCI(csr, imm) CSRRCI(REG_X0, csr, imm) // 立即数清除CSR
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// csrrwi csr, imm (Write CSR immediate)
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#define CSRRWI2(csr, imm) CSRRWI(REG_X0, csr, imm) // 立即数写入CSR
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// csrrsi csr, imm (Immediate set bits in CSR)
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#define CSRRSI2(csr, imm) CSRRSI(REG_X0, csr, imm) // 立即数置位CSR
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// csrrci csr, imm (Immediate clear bits in CSR)
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#define CSRRCI2(csr, imm) CSRRCI(REG_X0, csr, imm) // 立即数清除CSR
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// // frcsr rd (Read FP control/status register)
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// #define FRC SR(rd) CSRRS(rd, FCSR, REG_X0) // 读取FP控制/状态寄存器
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// // fscsr rs (Write FP control/status register)
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// #define FSCSR(rs) CSRRW(REG_X0, FCSR, rs) // 写入FP控制/状态寄存器
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// // frrm rd (Read FP rounding mode)
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// #define FRRM(rd) CSRRS(rd, FRM, REG_X0) // 读取FP舍入模式
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// // fsrm rs (Write FP rounding mode)
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// #define FS RM(rs) CSRRW(REG_X0, FRM, rs) // 写入FP舍入模式
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// // frflags rd (Read FP exception flags)
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// #define FRFLAGS(rd) CSRRS(rd, FFLAGS, REG_X0) // 读取FP例外标志
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// // fsflags rs (Write FP exception flags)
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// #define FS FLAGS(rs) CSRRW(REG_X0, FFLAGS, rs) // 写入FP例外标志
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// Myriad sequences
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#define LI(rd, num) \
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LUI(rd, num), \
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ADDI(rd, rd, num)
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#define MV(rd, rs) ADDI(rd, rs, 0)
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#define NOT(rd, rs) XORI(rd, rs, -1)
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#define SEQZ(rd, rs) SLTIU(rd, rs, 1)
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#define SGT(rd, rs1, rs2) SLT(rd, rs2, rs1)
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// TODO call have error when outof jalr
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#define CALL(offset) \
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AUIPC(REG_X1, REG_X0), \
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JALR(REG_X1, REG_X1, offset)
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#define CALL_ABS(addr) \
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AUIPC(REG_X0, addr), \
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JALR(REG_X1, REG_X0, addr)
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#ifdef RISCV_VM_BUILDIN_ECALL
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#define ECALL_PNT_INT(num) \
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ADDI(REG_A0, REG_X0, num), \
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ADDI(REG_A7, REG_X0, 0x1), \
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ECALL()
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#define ECALL_PNT_STR(str) \
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ADDI(REG_A0, REG_X0, str), \
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ADDI(REG_A7, REG_X0, 0x4), \
|
||
ECALL()
|
||
|
||
#define ECALL_EXIT2() \
|
||
ADDI(REG_A7, REG_X0, 93), \
|
||
ECALL()
|
||
|
||
#define ECALL_EXIT_ARG(errno) \
|
||
ADDI(REG_A0, REG_X0, errno), \
|
||
ECALL_EXIT2()
|
||
|
||
#define ECALL_EXIT() \
|
||
ADDI(REG_A7, REG_X0, 93), \
|
||
ECALL()
|
||
|
||
#define ECALL_SCAN_INT(int) \
|
||
ADDI(REG_A7, (1025 + 4)), \
|
||
ECALL()
|
||
|
||
#define ECALL_SCAN_STR(str) \
|
||
ADDI(REG_A0, REG_X0, str), \
|
||
ADDI(REG_A7, REG_X0, (1025 + 5)), \
|
||
ECALL()
|
||
#endif
|
||
|
||
#endif
|