#ifndef __SMCC_RISCV32_DEF_H__
#define __SMCC_RISCV32_DEF_H__

#include <lib/core.h>

typedef enum rv_ext {
    RV32_I_EXT,
    RV32_M_EXT,
} rv_ext_t;

typedef enum rv_fmt {
    RV_R_TYPE,
    RV_I_TYPE,
    RV_S_TYPE,
    RV_B_TYPE,
    RV_U_TYPE,
    RV_J_TYPE,
} rv_fmt_t;

typedef enum rv_instr_type {
    /* U type */
    RV_AUIPC,
    RV_LUI,
    /* J type */
    RV_JAL,
    /* I type */
    RV_JALR,
        // Load
    RV_LB,
    RV_LH,
    RV_LW,
    RV_LBU,
    RV_LHU,
        // Imm arithmetic
    RV_ADDI,
    RV_SLTI,
    RV_SLTIU,
    RV_XORI,
    RV_ORI,
    RV_ANDI,
        // Imm shift
    RV_SLLI,
    RV_SRLI,
    RV_SRAI,
    /* B type */
    RV_BEQ,
    RV_BNE,
    RV_BLT,
    RV_BGE,
    RV_BLTU,
    RV_BGEU,
    /* S type */
    RV_SB,
    RV_SH,
    RV_SW,
    /* R type */
    RV_ADD,
    RV_SUB,
    RV_SLL,
    RV_SLT,
    RV_SLTU,
    RV_XOR,
    RV_SRL,
    RV_SRA,
    RV_OR,
    RV_AND,
    /* I type (system) */
    RV_FENCE,
    RV_ECALL,
    RV_EBREAK,

    /* M-Extention */
    RV_MUL,
    RV_DIV,
    RV_REM,
    // RV_MULH,
    // RV_DIVU,
    // RV_REMU,
    // RV_MULHSU,
    // RV_MULHU,
    // RV_DIVU,
    // RV_REMU,
    // RV_MULHSU,
    // RV_MULHU,
    RV_INSTR_TYPE_COUNT,
} rv_instr_type_t;

typedef enum rv_reg {
    REG_X0,  REG_X1,  REG_X2,  REG_X3,  REG_X4,  REG_X5,  REG_X6,  REG_X7,
    REG_X8,  REG_X9,  REG_X10, REG_X11, REG_X12, REG_X13, REG_X14, REG_X15,
    REG_X16, REG_X17, REG_X18, REG_X19, REG_X20, REG_X21, REG_X22, REG_X23,
    REG_X24, REG_X25, REG_X26, REG_X27, REG_X28, REG_X29, REG_X30, REG_X31,
    REG_ZERO = REG_X0,  REG_RA = REG_X1, REG_SP = REG_X2, REG_GP = REG_X3,
    REG_TP = REG_X4,    REG_T0 = REG_X5, REG_T1 = REG_X6, REG_T2 = REG_X7,
    REG_S0 = REG_X8,    REG_S1 = REG_X9, REG_A0 = REG_X10, REG_A1 = REG_X11,
    REG_A2 = REG_X12,   REG_A3 = REG_X13, REG_A4 = REG_X14, REG_A5 = REG_X15,
    REG_A6 = REG_X16,   REG_A7 = REG_X17, REG_S2 = REG_X18, REG_S3 = REG_X19,
    REG_S4 = REG_X20,   REG_S5 = REG_X21, REG_S6 = REG_X22, REG_S7 = REG_X23,
    REG_S8 = REG_X24,   REG_S9 = REG_X25, REG_S10 = REG_X26, REG_S11 = REG_X27,
    REG_T3 = REG_X28,   REG_T4 = REG_X29, REG_T5 = REG_X30, REG_T6 = REG_X31,
    REG_NULL = 0,
} rv_reg_t;

#define RV_F3(f3) (f3 << 12)
#define RV_F7(f7) (f7 << 25)

typedef struct rv32_instr {
    rv_ext_t extention;
    rv_fmt_t format;
    rv_instr_type_t instr_type;
    const char* instr_name;
    u32_t instr;
    u32_t imm;
    rv_reg_t rd;
    rv_reg_t rs1;
    rv_reg_t rs2;
} rv32_instr_t;

#endif