diff --git a/src/mcode/riscv32/riscv32_def.h b/src/mcode/riscv32/riscv32_def.h
index 11c416a..349c769 100644
--- a/src/mcode/riscv32/riscv32_def.h
+++ b/src/mcode/riscv32/riscv32_def.h
@@ -116,4 +116,49 @@ typedef struct rv32_instr {
     rv_reg_t rs2;
 } rv32_instr_t;
 
+#define RV_INSTRUCTIONS \
+    X(RV32_I_EXT, RV_R_TYPE, RV_ADD,   "add",   0x33 | RV_F3(0x0) | RV_F7(0x00)) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_ADDI,  "addi",  0x13 | RV_F3(0x0)) \
+    X(RV32_I_EXT, RV_R_TYPE, RV_AND,   "and",   0x33 | RV_F3(0x7) | RV_F7(0x00)) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_ANDI,  "andi",  0x13 | RV_F3(0x7)) \
+    X(RV32_I_EXT, RV_U_TYPE, RV_AUIPC, "auipc", 0x17) \
+    X(RV32_I_EXT, RV_B_TYPE, RV_BEQ,   "beq",   0x63 | RV_F3(0x0)) \
+    X(RV32_I_EXT, RV_B_TYPE, RV_BGE,   "bge",   0x63 | RV_F3(0x5)) \
+    X(RV32_I_EXT, RV_B_TYPE, RV_BGEU,  "bgeu",  0x63 | RV_F3(0x7)) \
+    X(RV32_I_EXT, RV_B_TYPE, RV_BLT,   "blt",   0x63 | RV_F3(0x4)) \
+    X(RV32_I_EXT, RV_B_TYPE, RV_BLTU,  "bltu",  0x63 | RV_F3(0x6)) \
+    X(RV32_I_EXT, RV_B_TYPE, RV_BNE,   "bne",   0x63 | RV_F3(0x1)) \
+    X(RV32_M_EXT, RV_R_TYPE, RV_DIV,   "div",   0x33 | RV_F3(0x0) | RV_F7(0x05)) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_ECALL, "ecall", 0x73) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_EBREAK,"ebreak",0x100073) \
+    X(RV32_I_EXT, RV_J_TYPE, RV_JAL,   "jal",   0x6F) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_JALR,  "jalr",  0x67) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_LB,    "lb",    0x03 | RV_F3(0x0)) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_LBU,   "lbu",   0x03 | RV_F3(0x4)) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_LH,    "lh",    0x03 | RV_F3(0x1)) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_LHU,   "lhu",   0x03 | RV_F3(0x5)) \
+    X(RV32_I_EXT, RV_U_TYPE, RV_LUI,   "lui",   0x37) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_LW,    "lw",    0x03 | RV_F3(0x2)) \
+    X(RV32_M_EXT, RV_R_TYPE, RV_MUL,   "mul",   0x33 | RV_F3(0x0) | RV_F7(0x01)) \
+    X(RV32_I_EXT, RV_R_TYPE, RV_OR,    "or",    0x33 | RV_F3(0x6) | RV_F7(0x00)) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_ORI,   "ori",   0x13 | RV_F3(0x6)) \
+    X(RV32_M_EXT, RV_R_TYPE, RV_REM,   "rem",   0x33 | RV_F3(0x0) | RV_F7(0x07)) \
+    X(RV32_I_EXT, RV_S_TYPE, RV_SB,    "sb",    0x23 | RV_F3(0x0)) \
+    X(RV32_I_EXT, RV_R_TYPE, RV_SLL,   "sll",   0x33 | RV_F3(0x1) | RV_F7(0x00)) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_SLLI,  "slli",  0x13 | RV_F3(0x0)) \
+    X(RV32_I_EXT, RV_R_TYPE, RV_SLT,   "slt",   0x33 | RV_F3(0x2) | RV_F7(0x00)) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_SLTI,  "slti",  0x13 | RV_F3(0x2)) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_SLTIU, "sltiu", 0x13 | RV_F3(0x3)) \
+    X(RV32_I_EXT, RV_R_TYPE, RV_SLTU,  "sltu",  0x33 | RV_F3(0x3) | RV_F7(0x00)) \
+    X(RV32_I_EXT, RV_S_TYPE, RV_SH,    "sh",    0x23 | RV_F3(0x1)) \
+    X(RV32_I_EXT, RV_R_TYPE, RV_SRA,   "sra",   0x33 | RV_F3(0x5) | RV_F7(0x20)) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_SRAI,  "srai",  0x13 | RV_F3(0x5)) \
+    X(RV32_I_EXT, RV_R_TYPE, RV_SRL,   "srl",   0x33 | RV_F3(0x5) | RV_F7(0x00)) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_SRLI,  "srli",  0x13 | RV_F3(0x5)) \
+    X(RV32_I_EXT, RV_R_TYPE, RV_SUB,   "sub",   0x33 | RV_F3(0x0) | RV_F7(0x20)) \
+    X(RV32_I_EXT, RV_S_TYPE, RV_SW,    "sw",    0x23 | RV_F3(0x2)) \
+    X(RV32_I_EXT, RV_R_TYPE, RV_XOR,   "xor",   0x33 | RV_F3(0x4) | RV_F7(0x00)) \
+    X(RV32_I_EXT, RV_I_TYPE, RV_XORI,  "xori",  0x13 | RV_F3(0x4)) \
+    // End
+
 #endif
diff --git a/src/mcode/riscv32/riscv32_mcode.c b/src/mcode/riscv32/riscv32_mcode.c
index 065eafe..07ae5a2 100644
--- a/src/mcode/riscv32/riscv32_mcode.c
+++ b/src/mcode/riscv32/riscv32_mcode.c
@@ -1,59 +1,16 @@
 #include "riscv32_mcode.h"
 
 static const rv32_instr_t rv32_instrs[] = {
-    [RV_LUI] =      {RV32_I_EXT, RV_U_TYPE, RV_LUI,   "lui",   0x37},
-    [RV_AUIPC] =    {RV32_I_EXT, RV_U_TYPE, RV_AUIPC, "auipc", 0x17},
-
-    [RV_JAL] =      {RV32_I_EXT, RV_J_TYPE, RV_JAL,   "jal",   0x6F},
-
-    [RV_JALR] =     {RV32_I_EXT, RV_I_TYPE, RV_JALR,  "jalr",  0x67},
-
-    [RV_LB] =       {RV32_I_EXT, RV_I_TYPE, RV_LB,    "lb",    0x03 | RV_F3(0x0)},
-    [RV_LH] =       {RV32_I_EXT, RV_I_TYPE, RV_LH,    "lh",    0x03 | RV_F3(0x1)},
-    [RV_LW] =       {RV32_I_EXT, RV_I_TYPE, RV_LW,    "lw",    0x03 | RV_F3(0x2)},
-    [RV_LBU] =      {RV32_I_EXT, RV_I_TYPE, RV_LBU,   "lbu",   0x03 | RV_F3(0x4)},
-    [RV_LHU] =      {RV32_I_EXT, RV_I_TYPE, RV_LHU,   "lhu",   0x03 | RV_F3(0x5)},
-
-    [RV_ADDI] =     {RV32_I_EXT, RV_I_TYPE, RV_ADDI,  "addi",  0x13 | RV_F3(0x0)},
-    [RV_SLTI] =     {RV32_I_EXT, RV_I_TYPE, RV_SLTI,  "slti",  0x13 | RV_F3(0x2)},
-    [RV_SLTIU] =    {RV32_I_EXT, RV_I_TYPE, RV_SLTIU, "sltiu", 0x13 | RV_F3(0x3)},
-    [RV_XORI] =     {RV32_I_EXT, RV_I_TYPE, RV_XORI,  "xori",  0x13 | RV_F3(0x4)},
-    [RV_ORI] =      {RV32_I_EXT, RV_I_TYPE, RV_ORI,   "ori",   0x13 | RV_F3(0x6)},
-    [RV_ANDI] =     {RV32_I_EXT, RV_I_TYPE, RV_ANDI,  "andi",  0x13 | RV_F3(0x7)},
-
-    [RV_SLLI] =     {RV32_I_EXT, RV_I_TYPE, RV_SLLI,  "slli",  0x13 | RV_F3(0x0)},
-    [RV_SRLI] =     {RV32_I_EXT, RV_I_TYPE, RV_SRLI,  "srli",  0x13 | RV_F3(0x5)},
-    [RV_SRAI] =     {RV32_I_EXT, RV_I_TYPE, RV_SRAI,  "srai",  0x13 | RV_F3(0x5)},
-
-    [RV_BEQ] =      {RV32_I_EXT, RV_B_TYPE, RV_BEQ,   "beq",   0x63 | RV_F3(0x0)},
-    [RV_BNE] =      {RV32_I_EXT, RV_B_TYPE, RV_BNE,   "bne",   0x63 | RV_F3(0x1)},
-    [RV_BLT] =      {RV32_I_EXT, RV_B_TYPE, RV_BLT,   "blt",   0x63 | RV_F3(0x4)},
-    [RV_BGE] =      {RV32_I_EXT, RV_B_TYPE, RV_BGE,   "bge",   0x63 | RV_F3(0x5)},
-    [RV_BLTU] =     {RV32_I_EXT, RV_B_TYPE, RV_BLTU,  "bltu",  0x63 | RV_F3(0x6)},
-    [RV_BGEU] =     {RV32_I_EXT, RV_B_TYPE, RV_BGEU,  "bgeu",  0x63 | RV_F3(0x7)},
-
-    [RV_SB] =       {RV32_I_EXT, RV_S_TYPE, RV_SB,    "sb",    0x23 | RV_F3(0x0)},
-    [RV_SH] =       {RV32_I_EXT, RV_S_TYPE, RV_SH,    "sh",    0x23 | RV_F3(0x1)},
-    [RV_SW] =       {RV32_I_EXT, RV_S_TYPE, RV_SW,    "sw",    0x23 | RV_F3(0x2)},
-
-    [RV_ADD] =      {RV32_I_EXT, RV_R_TYPE, RV_ADD,   "add",   0x33 | RV_F3(0x0) | RV_F7(0x00)},
-    [RV_SUB] =      {RV32_I_EXT, RV_R_TYPE, RV_SUB,   "sub",   0x33 | RV_F3(0x0) | RV_F7(0x20)},
-    [RV_SLL] =      {RV32_I_EXT, RV_R_TYPE, RV_SLL,   "sll",   0x33 | RV_F3(0x1) | RV_F7(0x00)},
-    [RV_SLT] =      {RV32_I_EXT, RV_R_TYPE, RV_SLT,   "slt",   0x33 | RV_F3(0x2) | RV_F7(0x00)},
-    [RV_SLTU] =     {RV32_I_EXT, RV_R_TYPE, RV_SLTU,  "sltu",  0x33 | RV_F3(0x3) | RV_F7(0x00)},
-    [RV_XOR] =      {RV32_I_EXT, RV_R_TYPE, RV_XOR,   "xor",   0x33 | RV_F3(0x4) | RV_F7(0x00)},
-    [RV_SRL] =      {RV32_I_EXT, RV_R_TYPE, RV_SRL,   "srl",   0x33 | RV_F3(0x5) | RV_F7(0x00)},
-    [RV_SRA] =      {RV32_I_EXT, RV_R_TYPE, RV_SRA,   "sra",   0x33 | RV_F3(0x5) | RV_F7(0x20)},
-    [RV_OR] =       {RV32_I_EXT, RV_R_TYPE, RV_OR,    "or",    0x33 | RV_F3(0x6) | RV_F7(0x00)},
-    [RV_AND] =      {RV32_I_EXT, RV_R_TYPE, RV_AND,   "and",   0x33 | RV_F3(0x7) | RV_F7(0x00)},
-
-    // {RV32_I_EXT, RV_I_TYPE, RV_FENCE, "fence", 0x0F},
-    [RV_ECALL] =    {RV32_I_EXT, RV_I_TYPE, RV_ECALL, "ecall", 0x73},
-    [RV_EBREAK] =   {RV32_I_EXT, RV_I_TYPE, RV_EBREAK,"ebreak",0x100073},
-
-    [RV_MUL] =      {RV32_M_EXT, RV_R_TYPE, RV_MUL,   "mul",   0x33 | RV_F3(0x0) | RV_F7(0x01)},
-    [RV_DIV] =      {RV32_M_EXT, RV_R_TYPE, RV_DIV,   "div",   0x33 | RV_F3(0x0) | RV_F7(0x05)},
-    [RV_REM] =      {RV32_M_EXT, RV_R_TYPE, RV_REM,   "rem",   0x33 | RV_F3(0x0) | RV_F7(0x07)},
+    #define X(ext, fmt, type, name, op) \
+        [type] = { \
+            .extention = ext, \
+            .format = fmt, \
+            .instr_type = type, \
+            .instr_name = name, \
+            .instr = op \
+        },
+    RV_INSTRUCTIONS
+    #undef X
 };
 
 static inline int valid_reg(rv_reg_t reg) {