zzy
d2eafa9dc6
移除了对scc_abi包的依赖，将相关头文件从libs/abi移动到libs/ast2ir目录下。 重构了基本类型解析功能，将parse_base_type函数提取为独立的 scc_ast2ir_parse_base_type实现，并支持有符号/无符号类型区分。 feat(ast2ir): 实现整数常量表达式求值器 新增了完整的整数常量表达式求值功能，支持C11标准中的常量表达式规则， 包括字面量、标识符、sizeof/_Alignof、一元/二元运算、条件表达式和 类型转换等操作。该功能用于数组大小和枚举值的编译期计算验证。 refactor(ast2ir): 完善类型提升和算术转换机制 改进了整数提升和寻常算术转换的实现，修复了移位操作的符号处理问题， 添加了无符号比较操作的支持，增强了类型安全检查，统一了错误处理流程。 fix(ast2ir): 修复赋值表达式返回值和数组大小计算问题 修正了赋值表达式的返回值处理，确保返回右侧值而不是存储指令引用。 使用新的常量表达式求值器替代原有的硬编码数组大小计算，提高了 数组声明的正确性。
175 lines
6.7 KiB
C
175 lines
6.7 KiB
C
#include <arch/scc_x86_mir.h>
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static inline scc_x86_iform_t
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scc_mir_x86_mov_reg_mem(scc_x86_operand_value_t op0,
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scc_x86_operand_value_t op1) {
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Assert(op0.size == op1.size);
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Assert(op0.kind == SCC_X86_OPR_REG && op1.kind == SCC_X86_OPR_MEM);
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return op0.size == 1 ? SCC_X86_IFORM_MOV_GPR8_MEMB
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: SCC_X86_IFORM_MOV_GPRV_MEMV;
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}
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static inline scc_x86_iform_t
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scc_mir_x86_mov_reg_reg(scc_x86_operand_value_t op0,
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scc_x86_operand_value_t op1) {
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Assert(op0.size == op1.size);
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Assert(op0.kind == SCC_X86_OPR_REG && op1.kind == SCC_X86_OPR_REG);
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return op0.size == 1 ? SCC_X86_IFORM_MOV_GPR8_GPR8_8A
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: SCC_X86_IFORM_MOV_GPRV_GPRV_8B;
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}
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static inline scc_x86_iform_t
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scc_mir_x86_mov_reg_imm(scc_x86_operand_value_t op0,
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scc_x86_operand_value_t op1) {
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Assert(op0.size == op1.size);
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Assert(op0.kind == SCC_X86_OPR_REG && op1.kind == SCC_X86_OPR_IMM);
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return op0.size == 1 ? SCC_X86_IFORM_MOV_GPR8_IMMB_B0
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: SCC_X86_IFORM_MOV_GPRV_IMMV;
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}
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static inline scc_x86_iform_t
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scc_mir_x86_mov_mem_reg(scc_x86_operand_value_t op0,
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scc_x86_operand_value_t op1) {
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Assert(op0.size == op1.size);
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Assert(op0.kind == SCC_X86_OPR_MEM && op1.kind == SCC_X86_OPR_REG);
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return op0.size == 1 ? SCC_X86_IFORM_MOV_MEMB_GPR8
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: SCC_X86_IFORM_MOV_MEMV_GPRV;
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}
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static inline scc_x86_iform_t
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scc_mir_x86_mov_mem_imm(scc_x86_operand_value_t op0,
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scc_x86_operand_value_t op1) {
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Assert(op0.size == op1.size);
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Assert(op0.kind == SCC_X86_OPR_MEM && op1.kind == SCC_X86_OPR_IMM);
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return op0.size == 1 ? SCC_X86_IFORM_MOV_MEMB_IMMB
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: SCC_X86_IFORM_MOV_MEMV_IMMZ;
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}
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static inline u8 get_op_size(scc_x86_operand_value_t op, cbool get_value) {
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if (get_value) {
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return op.size;
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}
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if (op.kind == SCC_X86_OPR_MEM) {
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return 8;
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}
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if (op.kind == SCC_X86_OPR_RELOC && op.reloc.kind == SCC_X86_OPR_MEM) {
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return 8;
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}
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return op.size;
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}
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void scc_x86_emit_move_to_vec(scc_mir_x86_instr_vec_t *vec,
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scc_x86_operand_value_t dst,
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scc_x86_operand_value_t src) {
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u8 dst_size = get_op_size(dst, false);
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u8 src_size = get_op_size(src, false);
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if (dst_size != src_size) {
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LOG_FATAL("Mismatched register sizes for move %d != %d", dst_size,
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src_size);
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}
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scc_mir_x86_instr_t ins;
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if (dst.kind == SCC_X86_OPR_REG) {
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if (src.kind == SCC_X86_OPR_REG) {
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scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_reg_reg(dst, src), dst,
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src, scc_pos_create());
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} else if (src.kind == SCC_X86_OPR_IMM) {
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scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_reg_imm(dst, src), dst,
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src, scc_pos_create());
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} else if (src.kind == SCC_X86_OPR_MEM ||
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(src.kind == SCC_X86_OPR_RELOC &&
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src.reloc.target == SCC_X86_RELOC_TARGET_SYMBOL)) {
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Assert(dst_size == 8);
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scc_mir_x86_instr_2(&ins, SCC_X86_IFORM_LEA_GPRV_AGEN, dst, src,
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scc_pos_create());
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} else {
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Panic("emit_move: unsupported src kind %d", src.kind);
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}
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} else if (dst.kind == SCC_X86_OPR_MEM) {
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if (src.kind == SCC_X86_OPR_IMM) {
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scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_mem_imm(dst, src), dst,
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src, scc_pos_create());
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} else if (src.kind == SCC_X86_OPR_REG) {
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scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_mem_reg(dst, src), dst,
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src, scc_pos_create());
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} else {
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Panic("emit_move: unsupported src kind %d", src.kind);
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}
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} else {
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Panic("emit_move: unsupported dst kind %d", dst.kind);
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}
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scc_vec_push(*vec, ins);
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}
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void scc_x86_emit_load_to_vec(scc_mir_x86_instr_vec_t *vec,
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scc_x86_operand_value_t dst,
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scc_x86_operand_value_t src_addr) {
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u8 dst_size = get_op_size(dst, false);
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u8 src_addr_size = get_op_size(src_addr, true);
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if (dst_size != src_addr_size) {
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LOG_FATAL("Mismatched sizes for load %d != %d", dst_size,
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src_addr_size);
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}
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Assert(dst.kind == SCC_X86_OPR_REG);
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scc_x86_operand_value_t mem_op;
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if (src_addr.kind == SCC_X86_OPR_REG) {
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mem_op = (scc_x86_operand_value_t){
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.kind = SCC_X86_OPR_MEM,
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.mem =
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{
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.base = src_addr.reg,
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.index = SCC_X86_REG_INVALID,
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.scale = 1,
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.disp.displacement = 0,
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.disp.displacement_bits = src_addr_size * 8,
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},
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.size = src_addr_size,
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};
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} else if (src_addr.kind == SCC_X86_OPR_MEM) {
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mem_op = src_addr;
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} else {
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Panic("emit_load: src must be REG or MEM");
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}
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scc_mir_x86_instr_t ins;
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scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_reg_mem(dst, mem_op), dst, mem_op,
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scc_pos_create());
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scc_vec_push(*vec, ins);
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}
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void scc_x86_emit_store_to_vec(scc_mir_x86_instr_vec_t *vec,
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scc_x86_operand_value_t dst_addr,
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scc_x86_operand_value_t src) {
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u8 dst_addr_size = get_op_size(dst_addr, true);
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u8 src_size = get_op_size(src, false);
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if (dst_addr_size != src_size) {
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LOG_FATAL("Mismatched sizes for store %d != %d", dst_addr_size,
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src_size);
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}
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scc_x86_operand_value_t mem_op;
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if (dst_addr.kind == SCC_X86_OPR_REG) {
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mem_op = (scc_x86_operand_value_t){
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.kind = SCC_X86_OPR_MEM,
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.mem =
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{
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.base = dst_addr.reg,
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.index = SCC_X86_REG_INVALID,
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.scale = 1,
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.disp.displacement = 0,
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.disp.displacement_bits = dst_addr_size * 8,
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},
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.size = dst_addr_size,
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};
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} else if (dst_addr.kind == SCC_X86_OPR_MEM) {
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mem_op = dst_addr;
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} else {
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Panic("emit_store: dst_addr kind not supported %d", dst_addr.kind);
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}
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scc_mir_x86_instr_t ins;
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if (src.kind == SCC_X86_OPR_REG) {
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scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_mem_reg(mem_op, src), mem_op,
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src, scc_pos_create());
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} else if (src.kind == SCC_X86_OPR_IMM) {
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scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_mem_imm(mem_op, src), mem_op,
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src, scc_pos_create());
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} else {
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Panic("unsupported src kind not supported %d", src.kind);
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}
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scc_vec_push(*vec, ins);
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}
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