zzy
902ee6dea3
添加了对命令行参数枚举类型的支持，允许用户从预定义的选项中进行选择， 并在解析时进行验证。同时修复了空值检查问题。 refactor(mir): 重构pass管理系统 将原有的pass管理器系统简化为直接的pass执行函数，移除了复杂的 依赖管理和流水线构建机制，使系统更加简洁明了。 chore(ir): 添加Windows x64 ABI实现 实现了Windows x64平台的ABI约定，包括参数传递、寄存器使用和 栈帧布局的处理逻辑。 feat(config): 统一编译阶段控制配置 将多个独立的布尔类型编译阶段控制改为统一的枚举类型，便于 管理和扩展新的编译阶段。
487 lines
17 KiB
C
487 lines
17 KiB
C
#include <arch/x86_64_isel.h>
|
||
|
||
#include <x86/scc_x86_iform.c>
|
||
#include <x86/scc_x86_reg.c>
|
||
|
||
static const char *preg_name(int preg_id) {
|
||
if (preg_id < 1 || preg_id >= SCC_X86_REG_COUNT)
|
||
return "???";
|
||
return scc_x86_reg_table[preg_id].display_str;
|
||
}
|
||
|
||
void scc_x86_instr_dump(scc_tree_dump_t *td, const scc_mir_instr_t *instr) {
|
||
scc_x86_iform_t iform = instr->opcode;
|
||
const scc_x86_iform_info_t *info = &scc_x86_iform_table[iform];
|
||
scc_tree_dump_append_fmt(td, " %s", info->iform_name);
|
||
// Assert(instr->num_operands == info->num_ops);
|
||
for (int i = 0; i < instr->num_operands; i += 1) {
|
||
if (i == 0)
|
||
scc_tree_dump_append(td, " ");
|
||
else
|
||
scc_tree_dump_append_fmt(td, ", ");
|
||
scc_mir_operand_t *op = &instr->operands[i];
|
||
switch (op->kind) {
|
||
case SCC_MIR_OP_VREG:
|
||
scc_tree_dump_append_fmt(td, "$%d", op->vreg);
|
||
break;
|
||
case SCC_MIR_OP_PREG:
|
||
scc_tree_dump_append_fmt(td, "$%s", preg_name(op->preg));
|
||
break;
|
||
case SCC_MIR_OP_IMM:
|
||
scc_tree_dump_append_fmt(td, "%ld", op->imm);
|
||
break;
|
||
case SCC_MIR_OP_BLOCK:
|
||
scc_tree_dump_append_fmt(td, "#BB%d", op->block_id);
|
||
break;
|
||
case SCC_MIR_OP_SYMBOL:
|
||
scc_tree_dump_append_fmt(td, "@%s", op->symbol);
|
||
break;
|
||
case SCC_MIR_OP_MEM:
|
||
scc_tree_dump_append_fmt(td, "[%d]", op->stack_slot);
|
||
break;
|
||
default:
|
||
break;
|
||
}
|
||
}
|
||
}
|
||
|
||
// 将 LIR 值转换为 MIR 操作数
|
||
scc_mir_operand_t scc_x86_lir_val_to_mir_op(scc_x86_64_isel_t *isel,
|
||
const scc_lir_val_t *val) {
|
||
scc_mir_operand_t op = {0};
|
||
switch (val->kind) {
|
||
case SCC_LIR_INSTR_KIND_NONE:
|
||
op.kind = SCC_MIR_OP_NONE;
|
||
break;
|
||
case SCC_LIR_INSTR_KIND_VREG:
|
||
op.kind = SCC_MIR_OP_VREG;
|
||
op.vreg = val->data.reg;
|
||
break;
|
||
case SCC_LIR_INSTR_KIND_IMM:
|
||
op.kind = SCC_MIR_OP_IMM;
|
||
// FIXME hack ap
|
||
op.imm = val->data.imm.data.digit;
|
||
break;
|
||
case SCC_LIR_INSTR_KIND_FIMM:
|
||
// 浮点立即数暂时作为普通立即数处理（后端需特殊处理）
|
||
op.kind = SCC_MIR_OP_IMM;
|
||
op.imm = *(i64 *)&val->data.fimm;
|
||
break;
|
||
case SCC_LIR_INSTR_KIND_SYMBOL:
|
||
op.kind = SCC_MIR_OP_SYMBOL;
|
||
op.symbol = val->data.symbol;
|
||
break;
|
||
case SCC_LIR_INSTR_KIND_ARG:
|
||
Assert(isel->abi_lowering.lower_param);
|
||
op = isel->abi_lowering.lower_param(isel, val);
|
||
break;
|
||
default:
|
||
UNREACHABLE();
|
||
}
|
||
return op;
|
||
}
|
||
|
||
// 虚拟临时寄存器分配（简单递增）
|
||
static scc_mir_operand_t new_vreg_temp(scc_x86_64_isel_t *isel) {
|
||
return (scc_mir_operand_t){.kind = SCC_MIR_OP_VREG,
|
||
.vreg = isel->func_meta->vregs_count++};
|
||
}
|
||
|
||
void scc_x86_emit_move(scc_x86_64_isel_t *isel, scc_mir_operand_t dst,
|
||
scc_mir_operand_t src, u8 size) {
|
||
if (dst.kind == SCC_MIR_OP_VREG || dst.kind == SCC_MIR_OP_PREG) {
|
||
if (src.kind == SCC_MIR_OP_VREG || src.kind == SCC_MIR_OP_PREG) {
|
||
add_instr_2(isel, SCC_X86_IFORM_MOV_GPRV_GPRV_89, dst, src);
|
||
} else if (src.kind == SCC_MIR_OP_IMM) {
|
||
add_instr_2(isel,
|
||
(size == 8) ? SCC_X86_IFORM_MOV_GPRV_IMMZ
|
||
: SCC_X86_IFORM_MOV_GPRV_IMMV,
|
||
dst, src);
|
||
} else if (src.kind == SCC_MIR_OP_SYMBOL) {
|
||
add_instr_2(isel, SCC_X86_IFORM_MOV_GPRV_IMMZ, dst, src);
|
||
} else if (src.kind == SCC_MIR_OP_MEM) {
|
||
add_instr_2(isel, SCC_X86_IFORM_MOV_GPRV_MEMV, dst, src);
|
||
} else {
|
||
UNREACHABLE();
|
||
}
|
||
} else if (dst.kind == SCC_MIR_OP_MEM) {
|
||
if (src.kind == SCC_MIR_OP_VREG || src.kind == SCC_MIR_OP_PREG) {
|
||
add_instr_2(isel, SCC_X86_IFORM_MOV_MEMV_GPRV, dst, src);
|
||
} else if (src.kind == SCC_MIR_OP_IMM) {
|
||
add_instr_2(isel, SCC_X86_IFORM_MOV_MEMV_IMMZ, dst, src);
|
||
} else if (src.kind == SCC_MIR_OP_SYMBOL) {
|
||
scc_mir_operand_t temp = new_vreg_temp(isel);
|
||
add_instr_2(isel, SCC_X86_IFORM_MOV_GPRV_IMMZ, temp, src);
|
||
add_instr_2(isel, SCC_X86_IFORM_MOV_MEMV_GPRV, dst, temp);
|
||
} else if (src.kind == SCC_MIR_OP_MEM) {
|
||
scc_mir_operand_t temp = new_vreg_temp(isel);
|
||
scc_x86_emit_move(isel, temp, src, size);
|
||
scc_x86_emit_move(isel, dst, temp, size);
|
||
} else {
|
||
UNREACHABLE();
|
||
}
|
||
} else {
|
||
UNREACHABLE();
|
||
}
|
||
}
|
||
|
||
static void emit_compare(scc_x86_64_isel_t *isel, scc_mir_operand_t op0,
|
||
scc_mir_operand_t op1, u8 size) {
|
||
// cmp op0, op1 (注意 x86 是 cmp a, b 即 a - b)
|
||
if (op0.kind == SCC_MIR_OP_VREG && op1.kind == SCC_MIR_OP_IMM) {
|
||
add_instr_2(isel, SCC_X86_IFORM_CMP_GPRV_IMMZ, op0, op1);
|
||
} else if (op0.kind == SCC_MIR_OP_VREG && op1.kind == SCC_MIR_OP_VREG) {
|
||
add_instr_2(isel, SCC_X86_IFORM_CMP_GPRV_GPRV_39, op0, op1);
|
||
} else {
|
||
UNREACHABLE();
|
||
}
|
||
}
|
||
|
||
/* 条件码到 setcc 指令的映射 */
|
||
static scc_x86_iform_t cond_to_setcc(scc_lir_cond_t cond) {
|
||
switch (cond) {
|
||
case SCC_LIR_COND_EQ:
|
||
return SCC_X86_IFORM_SETZ_GPR8;
|
||
case SCC_LIR_COND_NE:
|
||
return SCC_X86_IFORM_SETNZ_GPR8;
|
||
case SCC_LIR_COND_SLT:
|
||
return SCC_X86_IFORM_SETL_GPR8;
|
||
case SCC_LIR_COND_SLE:
|
||
return SCC_X86_IFORM_SETLE_GPR8;
|
||
case SCC_LIR_COND_SGT:
|
||
return SCC_X86_IFORM_SETNLE_GPR8; // SETG
|
||
case SCC_LIR_COND_SGE:
|
||
return SCC_X86_IFORM_SETNL_GPR8; // SETGE
|
||
case SCC_LIR_COND_ULT:
|
||
return SCC_X86_IFORM_SETB_GPR8;
|
||
case SCC_LIR_COND_ULE:
|
||
return SCC_X86_IFORM_SETBE_GPR8;
|
||
case SCC_LIR_COND_UGT:
|
||
return SCC_X86_IFORM_SETNBE_GPR8; // SETA
|
||
case SCC_LIR_COND_UGE:
|
||
return SCC_X86_IFORM_SETNB_GPR8; // SETAE
|
||
default:
|
||
UNREACHABLE();
|
||
}
|
||
}
|
||
|
||
static void emit_copy_if_needed(scc_x86_64_isel_t *isel, scc_mir_operand_t dst,
|
||
scc_mir_operand_t src0, u8 size) {
|
||
if (dst.kind == SCC_MIR_OP_VREG && src0.kind == SCC_MIR_OP_VREG &&
|
||
dst.vreg == src0.vreg) {
|
||
return;
|
||
}
|
||
scc_x86_emit_move(isel, dst, src0, size);
|
||
}
|
||
|
||
static void emit_binary_op(scc_x86_64_isel_t *isel, scc_lir_op_t op,
|
||
scc_mir_operand_t dst, scc_mir_operand_t src0,
|
||
scc_mir_operand_t src1, u8 size) {
|
||
emit_copy_if_needed(isel, dst, src0, size);
|
||
|
||
bool is_imm = (src1.kind == SCC_MIR_OP_IMM);
|
||
scc_x86_iform_t iform;
|
||
switch (op) {
|
||
case SCC_LIR_ADD:
|
||
iform = is_imm ? SCC_X86_IFORM_ADD_GPRV_IMMZ
|
||
: SCC_X86_IFORM_ADD_GPRV_GPRV_01;
|
||
break;
|
||
case SCC_LIR_SUB:
|
||
iform = is_imm ? SCC_X86_IFORM_SUB_GPRV_IMMZ
|
||
: SCC_X86_IFORM_SUB_GPRV_GPRV_29;
|
||
break;
|
||
case SCC_LIR_AND:
|
||
iform = is_imm ? SCC_X86_IFORM_AND_GPRV_IMMZ
|
||
: SCC_X86_IFORM_AND_GPRV_GPRV_21;
|
||
break;
|
||
case SCC_LIR_OR:
|
||
iform =
|
||
is_imm ? SCC_X86_IFORM_OR_GPRV_IMMZ : SCC_X86_IFORM_OR_GPRV_GPRV_09;
|
||
break;
|
||
case SCC_LIR_XOR:
|
||
iform = is_imm ? SCC_X86_IFORM_XOR_GPRV_IMMZ
|
||
: SCC_X86_IFORM_XOR_GPRV_GPRV_31;
|
||
break;
|
||
default:
|
||
UNREACHABLE();
|
||
}
|
||
add_instr_2(isel, iform, dst, src1);
|
||
}
|
||
|
||
static scc_mir_operand_t stack_slot_op(int offset) {
|
||
return (scc_mir_operand_t){.kind = SCC_MIR_OP_MEM, .stack_slot = offset};
|
||
}
|
||
|
||
static void emit_spill_load(scc_x86_64_isel_t *isel, int vreg, int offset) {
|
||
scc_mir_operand_t dst = {.kind = SCC_MIR_OP_VREG, .vreg = vreg};
|
||
add_instr_2(isel, SCC_X86_IFORM_MOV_GPRV_MEMV, dst, stack_slot_op(offset));
|
||
}
|
||
|
||
static void emit_spill_store(scc_x86_64_isel_t *isel, int vreg, int offset) {
|
||
scc_mir_operand_t src = {.kind = SCC_MIR_OP_VREG, .vreg = vreg};
|
||
add_instr_2(isel, SCC_X86_IFORM_MOV_MEMV_GPRV, stack_slot_op(offset), src);
|
||
}
|
||
|
||
static void emit_alloca(scc_x86_64_isel_t *isel, scc_mir_operand_t dst,
|
||
i64 size) {
|
||
scc_mir_operand_t imm = {.kind = SCC_MIR_OP_IMM, .imm = size};
|
||
scc_mir_operand_t rsp = {.kind = SCC_MIR_OP_PREG, .preg = SCC_X86_REG_RSP};
|
||
add_instr_2(isel, SCC_X86_IFORM_SUB_GPRV_IMMZ, rsp, imm);
|
||
scc_x86_emit_move(isel, dst, rsp, 8);
|
||
}
|
||
|
||
static void sel_mir(scc_x86_64_isel_t *isel, const scc_lir_instr_t *instr) {
|
||
scc_mir_operand_t dst = scc_x86_lir_val_to_mir_op(isel, &instr->to);
|
||
scc_mir_operand_t src0 = scc_x86_lir_val_to_mir_op(isel, &instr->arg0);
|
||
scc_mir_operand_t src1 = scc_x86_lir_val_to_mir_op(isel, &instr->arg1);
|
||
u8 size = instr->size;
|
||
|
||
switch (instr->op) {
|
||
/* ---- 数据移动 ---- */
|
||
case SCC_LIR_MOV:
|
||
scc_x86_emit_move(isel, dst, src0, size);
|
||
break;
|
||
|
||
case SCC_LIR_LOAD:
|
||
// 从 [addr] 加载到 vreg（addr 通常为 vreg）
|
||
add_instr_2(isel, SCC_X86_IFORM_MOV_GPRV_MEMV, dst, src0);
|
||
break;
|
||
|
||
case SCC_LIR_STORE_ADDR:
|
||
TODO();
|
||
break;
|
||
case SCC_LIR_STORE:
|
||
// 将 src0 存入 [src1]
|
||
add_instr_2(isel, SCC_X86_IFORM_MOV_MEMV_GPRV, src1, src0);
|
||
break;
|
||
|
||
case SCC_LIR_LEA:
|
||
case SCC_LIR_LOAD_ADDR:
|
||
// 地址计算，src0 是复杂地址（LIR 的 MEM 类型）
|
||
add_instr_2(isel, SCC_X86_IFORM_LEA_GPRV_AGEN, dst, src0);
|
||
break;
|
||
|
||
/* ---- 一元运算 ---- */
|
||
case SCC_LIR_NEG:
|
||
add_instr_1(isel, SCC_X86_IFORM_NEG_GPRV, dst);
|
||
break;
|
||
case SCC_LIR_NOT:
|
||
add_instr_1(isel, SCC_X86_IFORM_NOT_GPRV, dst);
|
||
break;
|
||
|
||
/* ---- 算术/逻辑二元运算 ---- */
|
||
case SCC_LIR_ADD:
|
||
case SCC_LIR_SUB:
|
||
case SCC_LIR_AND:
|
||
case SCC_LIR_OR:
|
||
case SCC_LIR_XOR:
|
||
emit_binary_op(isel, instr->op, dst, src0, src1, size);
|
||
break;
|
||
|
||
case SCC_LIR_MUL:
|
||
// imul dst, src0, src1 → 需要 mov + imul
|
||
emit_copy_if_needed(isel, dst, src0, size);
|
||
add_instr_2(isel, SCC_X86_IFORM_IMUL_GPRV_GPRV, dst, src1);
|
||
break;
|
||
|
||
case SCC_LIR_SHL:
|
||
case SCC_LIR_SHR:
|
||
case SCC_LIR_SAR: {
|
||
// 双地址：dst = dst op count
|
||
emit_copy_if_needed(isel, dst, src0, size);
|
||
|
||
if (src1.kind == SCC_MIR_OP_IMM) {
|
||
scc_x86_iform_t iform;
|
||
switch (instr->op) {
|
||
case SCC_LIR_SHL:
|
||
iform = SCC_X86_IFORM_SHL_GPRV_IMMB_C1R4;
|
||
break;
|
||
case SCC_LIR_SHR:
|
||
iform = SCC_X86_IFORM_SHR_GPRV_IMMB;
|
||
break;
|
||
case SCC_LIR_SAR:
|
||
iform = SCC_X86_IFORM_SAR_GPRV_IMMB;
|
||
break;
|
||
default:
|
||
UNREACHABLE();
|
||
}
|
||
add_instr_2(isel, iform, dst, src1);
|
||
} else {
|
||
// 移位量在 CL（需要先 mov cl, src1）
|
||
scc_mir_operand_t cl = {.kind = SCC_MIR_OP_PREG,
|
||
.preg = SCC_X86_REG_CL};
|
||
scc_x86_emit_move(isel, cl, src1, 1); // CL 是 8 位
|
||
scc_x86_iform_t iform;
|
||
switch (instr->op) {
|
||
case SCC_LIR_SHL:
|
||
iform = SCC_X86_IFORM_SHL_GPRV_CL_D3R4;
|
||
break;
|
||
case SCC_LIR_SHR:
|
||
iform = SCC_X86_IFORM_SHR_GPRV_CL;
|
||
break;
|
||
case SCC_LIR_SAR:
|
||
iform = SCC_X86_IFORM_SAR_GPRV_CL;
|
||
break;
|
||
default:
|
||
UNREACHABLE();
|
||
}
|
||
add_instr_2(isel, iform, dst, cl);
|
||
}
|
||
} break;
|
||
|
||
/* ---- 除法与取模 ---- */
|
||
case SCC_LIR_DIV_S:
|
||
case SCC_LIR_DIV_U:
|
||
case SCC_LIR_REM_S:
|
||
case SCC_LIR_REM_U: {
|
||
scc_mir_operand_t rax = {.kind = SCC_MIR_OP_PREG,
|
||
.preg = SCC_X86_REG_RAX};
|
||
scc_mir_operand_t rdx = {.kind = SCC_MIR_OP_PREG,
|
||
.preg = SCC_X86_REG_RDX};
|
||
|
||
scc_x86_emit_move(isel, rax, src0, size);
|
||
|
||
if (instr->op == SCC_LIR_DIV_S || instr->op == SCC_LIR_REM_S) {
|
||
// 有符号扩展：cqo / cdq（根据 size 选择，这里简化为 64 位 cqo）
|
||
add_instr_0(isel, SCC_X86_IFORM_CQO);
|
||
} else {
|
||
// 无符号：xor edx, edx
|
||
scc_mir_operand_t zero = {.kind = SCC_MIR_OP_IMM, .imm = 0};
|
||
scc_x86_emit_move(isel, rdx, zero, size);
|
||
}
|
||
|
||
scc_x86_iform_t div_if =
|
||
(instr->op == SCC_LIR_DIV_S || instr->op == SCC_LIR_REM_S)
|
||
? SCC_X86_IFORM_IDIV_GPRV
|
||
: SCC_X86_IFORM_DIV_GPRV;
|
||
add_instr_1(isel, div_if, src1);
|
||
|
||
// 结果：商在 RAX，余数在 RDX
|
||
if (instr->op == SCC_LIR_REM_S || instr->op == SCC_LIR_REM_U)
|
||
scc_x86_emit_move(isel, dst, rdx, size);
|
||
else
|
||
scc_x86_emit_move(isel, dst, rax, size);
|
||
} break;
|
||
|
||
/* ---- 比较指令 ---- */
|
||
case SCC_LIR_CMP: {
|
||
// 1. 比较并设置标志位
|
||
if (src0.kind == SCC_MIR_OP_VREG && src1.kind == SCC_MIR_OP_IMM)
|
||
add_instr_2(isel, SCC_X86_IFORM_CMP_GPRV_IMMZ, src0, src1);
|
||
else if (src0.kind == SCC_MIR_OP_VREG && src1.kind == SCC_MIR_OP_VREG)
|
||
add_instr_2(isel, SCC_X86_IFORM_CMP_GPRV_GPRV_39, src0, src1);
|
||
else
|
||
UNREACHABLE();
|
||
|
||
// 2. 标志位 -> 布尔值 (写入 dst)
|
||
scc_x86_iform_t setcc = cond_to_setcc(instr->metadata.cond);
|
||
add_instr_1(isel, setcc, dst); // 注意 setcc 只写低 8 位
|
||
// 若需 32/64 位布尔值，可再 movzx dst, dst
|
||
if (size > 1) {
|
||
// movzx dst, dst (假设 MOVZX_GPRV_GPR8 存在；这里临时用 and 模拟)
|
||
// 简单处理：用 and dst, 1 清理高位
|
||
scc_mir_operand_t one = {.kind = SCC_MIR_OP_IMM, .imm = 1};
|
||
add_instr_2(isel, SCC_X86_IFORM_AND_GPRV_IMMZ, dst, one);
|
||
}
|
||
} break;
|
||
|
||
/* ---- 条件分支 ---- */
|
||
case SCC_LIR_BR: {
|
||
// arg0 是 CMP 产生的布尔值 (0 或 1)
|
||
// test src0, src0 ; jnz true_bb ; jmp false_bb
|
||
scc_mir_operand_t true_bb = {.kind = SCC_MIR_OP_BLOCK,
|
||
.block_id =
|
||
instr->metadata.br.true_target};
|
||
scc_mir_operand_t false_bb = {.kind = SCC_MIR_OP_BLOCK,
|
||
.block_id =
|
||
instr->metadata.br.false_target};
|
||
|
||
// test src0, src0
|
||
add_instr_2(isel, SCC_X86_IFORM_TEST_GPRV_GPRV, src0, src0);
|
||
// jnz true
|
||
add_instr_1(isel, SCC_X86_IFORM_JNZ_RELBRZ, true_bb);
|
||
// jmp false
|
||
add_instr_1(isel, SCC_X86_IFORM_JMP_RELBRZ, false_bb);
|
||
} break;
|
||
|
||
case SCC_LIR_JMP: {
|
||
add_instr_1(
|
||
isel, SCC_X86_IFORM_JMP_RELBRZ,
|
||
(scc_mir_operand_t){.kind = SCC_MIR_OP_BLOCK,
|
||
.block_id = instr->metadata.jmp_target});
|
||
} break;
|
||
|
||
/* ---- 栈分配 ---- */
|
||
case SCC_LIR_ALLOCA:
|
||
// emit_alloca(isel, dst, instr->metadata.alloca.size_bytes);
|
||
add_instr_2(isel, (scc_x86_iform_t)SCC_MIR_PSUEDO_ALLOCA,
|
||
scc_x86_lir_val_to_mir_op(isel, &instr->to),
|
||
(scc_mir_operand_t){
|
||
.kind = SCC_MIR_OP_IMM,
|
||
.imm = instr->size,
|
||
});
|
||
break;
|
||
|
||
/* ---- 其他（占位） ---- */
|
||
case SCC_LIR_NOP:
|
||
break;
|
||
|
||
/* ---- 调用与返回 ---- */
|
||
case SCC_LIR_CALL: {
|
||
Assert(isel->abi_lowering.lower_call);
|
||
isel->abi_lowering.lower_call(isel, instr);
|
||
} break;
|
||
case SCC_LIR_RET: {
|
||
Assert(isel->abi_lowering.lower_ret);
|
||
isel->abi_lowering.lower_ret(isel, instr);
|
||
} break;
|
||
default: {
|
||
UNREACHABLE();
|
||
} break;
|
||
}
|
||
}
|
||
|
||
static void sel_func(const scc_lir_module_t *lir_module,
|
||
const scc_lir_func_t *func) {
|
||
scc_x86_64_isel_t isel;
|
||
|
||
void scc_win_pc_x64_abi_lowering(scc_abi_lowering_t * abi_lowering);
|
||
// TODO target got real abi_lowering
|
||
isel.abi_lowering = (scc_abi_lowering_t){0};
|
||
scc_win_pc_x64_abi_lowering(&isel.abi_lowering);
|
||
|
||
isel.func_meta = SCC_LIR_FUNC_META(func);
|
||
scc_vec_foreach(func->bblocks, i) {
|
||
scc_vec_init(isel.instrs);
|
||
|
||
scc_cfg_bblock_id_t id = scc_vec_at(func->bblocks, i);
|
||
scc_cfg_bblock_t *bb =
|
||
scc_cfg_module_unsafe_get_bblock(&lir_module->cfg_module, id);
|
||
scc_lir_instr_vec_t *instrs = SCC_LIR_BBLOCK_VALUES(bb);
|
||
scc_vec_foreach(*instrs, i) {
|
||
const scc_lir_instr_t *ins = &scc_vec_at(*instrs, i);
|
||
sel_mir(&isel, ins);
|
||
}
|
||
|
||
bb->values = *(scc_cfg_value_vec_t *)&isel.instrs;
|
||
scc_vec_init(isel.instrs);
|
||
}
|
||
}
|
||
|
||
void scc_isel_x86_64(scc_mir_module_t *mir_module,
|
||
const scc_lir_module_t *lir_module) {
|
||
scc_vec_foreach(lir_module->cfg_module.funcs, i) {
|
||
if (i == 0)
|
||
continue;
|
||
scc_lir_func_t *func = &scc_vec_at(lir_module->cfg_module.funcs, i);
|
||
|
||
scc_mir_func_meta_t *func_meta =
|
||
scc_malloc(sizeof(scc_mir_func_meta_t));
|
||
Assert(func_meta != nullptr);
|
||
scc_mir_func_meta_init(func_meta);
|
||
scc_vec_push(mir_module->func_metas, func_meta);
|
||
sel_func(lir_module, func);
|
||
func->meta = func_meta;
|
||
}
|
||
}
|