zzy
68eac24152
- 修改x86_64_isel.h接口，将func_meta替换为func指针，并添加新的isel函数原型 - 添加x86_64_reg_alloc.h头文件，提供架构特定的寄存器分配操作填充函数 - 更新frame_layout.h定义frame_layout上下文结构 - 重构reg_alloc.h中的寄存器分配操作结构体，将ops从指针改为值类型， 并将mark_reg_unused重命名为clean_mark_regs - 扩展scc_mir.h中的函数元数据，添加vregs_count字段和虚拟寄存器管理函数 - 重新定义MIR pass阶段枚举，添加FRAME_LAYOUT和PROLOGUE_EPILOGUE阶段 - 添加win64目标相关头文件和实现，提供Windows x64 ABI降低和寄存器分配填充 - 更新虚拟寄存器表示格式从$到%，修复alloca指令处理 - 重构寄存器分配算法，改进虚拟寄存器到物理寄存器/栈槽的映射机制 - 完善MIR pass调度，支持多阶段处理流程
84 lines
2.7 KiB
C
84 lines
2.7 KiB
C
#include <arch/x86_64_isel.h>
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#include <arch/x86_64_reg_alloc.h>
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static void x86_emit_spill(scc_mir_instr_vec_t *ctx, int preg, int slot) {
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scc_mir_instr_t ins = {
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.opcode = SCC_X86_IFORM_MOV_MEMV_GPRV,
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.num_operands = 2,
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.operands = {{.kind = SCC_MIR_OP_MEM, .stack_slot = slot},
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{.kind = SCC_MIR_OP_PREG, .preg = preg}}};
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scc_vec_push(*ctx, ins);
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}
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static void x86_emit_reload(scc_mir_instr_vec_t *ctx, int preg, int slot) {
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scc_mir_instr_t ins = {
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.opcode = SCC_X86_IFORM_MOV_GPRV_MEMV,
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.num_operands = 2,
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.operands = {{.kind = SCC_MIR_OP_PREG, .preg = preg},
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{.kind = SCC_MIR_OP_MEM, .stack_slot = slot}}};
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scc_vec_push(*ctx, ins);
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}
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static void x86_emit_copy(scc_mir_instr_vec_t *ctx, int dst_preg, int src_preg,
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int size) {
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scc_mir_instr_t ins = {
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.opcode = SCC_X86_IFORM_MOV_GPRV_GPRV_89,
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.num_operands = 2,
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.operands = {{.kind = SCC_MIR_OP_PREG, .preg = dst_preg},
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{.kind = SCC_MIR_OP_PREG, .preg = src_preg}}};
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scc_vec_push(*ctx, ins);
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}
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/* ---- 临时寄存器 ---- */
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static int x86_acquire_temp_reg(void *vctx) { return SCC_X86_REG_R11; }
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static void x86_release_temp_reg(void *vctx, int preg) { /* 简单模式无需操作 */
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}
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/* ---- 操作数读写属性 ---- */
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static scc_op_access_t x86_get_operand_access(void *vctx, int opcode,
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int op_idx) {
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switch (opcode) {
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default:
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return SCC_REG_ALLOC_OP_ACCESS_READWRITE; // 保守
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}
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}
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/* ---- 隐式寄存器 ---- */
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static void x86_get_implicit_regs(void *vctx, int opcode, const int **uses,
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const int **defs) {
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static const int empty[] = {-1};
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static const int rax[] = {SCC_X86_REG_RAX, -1};
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static const int rdx[] = {SCC_X86_REG_RDX, -1};
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static const int rax_rdx[] = {SCC_X86_REG_RAX, SCC_X86_REG_RDX, -1};
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static const int cl[] = {SCC_X86_REG_CL, -1};
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switch (opcode) {
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case SCC_X86_IFORM_IDIV_GPRV:
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case SCC_X86_IFORM_DIV_GPRV:
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*uses = rax_rdx;
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*defs = rax_rdx;
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break;
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case SCC_X86_IFORM_CQO:
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*uses = rax;
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*defs = rax_rdx;
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break;
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case SCC_X86_IFORM_SAR_GPRV_CL:
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*uses = cl;
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*defs = empty;
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break;
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default:
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*uses = empty;
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*defs = empty;
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break;
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}
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}
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void scc_reg_alloc_fill_arch_x86(scc_reg_alloc_op_t *ops) {
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ops->emit_spill = x86_emit_spill;
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ops->emit_reload = x86_emit_reload;
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ops->emit_copy = x86_emit_copy;
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ops->get_operand_access = x86_get_operand_access;
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ops->get_implicit_regs = x86_get_implicit_regs;
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}
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