zzy/scc
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

feat(compiler): 实现HIR到LIR的函数定义标记和直接/间接调用区分

Browse Source 
- 在HIR函数元数据中添加defined字段来标记函数是否已定义
- 在AST到IR转换过程中设置函数定义状态
- 修改LIR模块函数声明接口以支持定义状态参数
- 实现直接调用和间接调用的区别处理，通过符号查找确定调用类型
- 更新LIR调用指令结构以支持直接和间接调用的不同表示方式
- 调整x86后端指令选择以正确处理不同类型的调用

fix(x86-isel): 优化x86指令发射和操作数大小处理

- 移除move/load/store函数中的size参数，改由操作数本身携带大小信息
- 简化x86指令操作数结构，减少操作数数量限制
- 添加专门的mov系列表单选择函数，根据操作数类型和大小自动选择正确的指令形式
- 修正间接调用的指令形式为CALL_NEAR_MEMV而非GPRV
- 添加向量版本的load/store/move发射函数

refactor(reg-alloc): 更新寄存器分配迭代器接口

- 为分配迭代器的替换方法添加size参数，以便正确处理不同大小的寄存器
This commit is contained in:
zzy
2026-05-23 15:33:54 +08:00
parent d78b91894e
commit ea553718f0
21 changed files with 495 additions and 444 deletions
Download Patch File Download Diff File Expand all files Collapse all files

78
libs/ir/mir/include/arch/scc_x86_mir.h
View File

@@ -9,16 +9,12 @@
#include <x86/scc_x86_reg.h>
typedef struct {
union {
int opcode;
scc_x86_iform_t iform;
};
u8 num_operands;
scc_x86_operand_value_t operands[6];
scc_x86_iform_t opcode; // must be int or enum
int num_operands;
scc_x86_operand_value_t operands[3];
scc_pos_t src_loc;
} scc_x86_instr_t;
// x86 后端指令：首字段 int opcode（正 = scc_x86_iform_t，负 = 伪指令）
typedef union scc_mir_x86_instr {
scc_mir_instr_t instr;
scc_x86_instr_t x86_instr;
@@ -26,8 +22,6 @@ typedef union scc_mir_x86_instr {
typedef SCC_VEC(scc_mir_x86_instr_t) scc_mir_x86_instr_vec_t;
// ── 基本块 values 强制转换 ──────────────────────────────────────────────
#define SCC_MIR_X86_BBLOCK_INSTRS(bb) ((scc_mir_x86_instr_vec_t *)&bb->values)
#define SCC_MIR_X86_BBLOCK_INSTRS_C(bb) \
((const scc_mir_x86_instr_vec_t *)&bb->values)
@@ -51,13 +45,14 @@ static inline void scc_x86_op_set_preg(scc_x86_operand_value_t *op,
}
// slot_id 编码为 base=INVALID, disp=slot_id
static inline scc_x86_operand_value_t scc_x86_op_slot(int slot_id) {
static inline scc_x86_operand_value_t scc_x86_op_slot(int slot_id, u8 size) {
scc_x86_operand_value_t o = {.kind = SCC_X86_OPR_MEM};
o.mem.base = SCC_X86_REG_INVALID;
o.mem.index = SCC_X86_REG_INVALID;
o.mem.scale = 1;
o.mem.disp.displacement = slot_id;
o.mem.disp.displacement_bits = 0;
o.size = size;
return o;
}
@@ -68,13 +63,14 @@ static inline int scc_x86_op_slot_id(const scc_x86_operand_value_t *op) {
return op->mem.disp.displacement;
}
static inline void scc_mir_x86_instr_0(scc_mir_x86_instr_t *out, int opcode,
scc_pos_t pos) {
static inline void scc_mir_x86_instr_0(scc_mir_x86_instr_t *out,
scc_x86_iform_t opcode, scc_pos_t pos) {
out->x86_instr.opcode = opcode;
out->x86_instr.num_operands = 0;
out->x86_instr.src_loc = pos;
}
static inline void scc_mir_x86_instr_1(scc_mir_x86_instr_t *out, int opcode,
static inline void scc_mir_x86_instr_1(scc_mir_x86_instr_t *out,
scc_x86_iform_t opcode,
scc_x86_operand_value_t op0,
scc_pos_t pos) {
out->x86_instr.opcode = opcode;
@@ -82,7 +78,8 @@ static inline void scc_mir_x86_instr_1(scc_mir_x86_instr_t *out, int opcode,
out->x86_instr.operands[0] = op0;
out->x86_instr.src_loc = pos;
}
static inline void scc_mir_x86_instr_2(scc_mir_x86_instr_t *out, int opcode,
static inline void scc_mir_x86_instr_2(scc_mir_x86_instr_t *out,
scc_x86_iform_t opcode,
scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1,
scc_pos_t pos) {
@@ -92,11 +89,10 @@ static inline void scc_mir_x86_instr_2(scc_mir_x86_instr_t *out, int opcode,
out->x86_instr.operands[1] = op1;
out->x86_instr.src_loc = pos;
}
static inline void scc_mir_x86_instr_3(scc_mir_x86_instr_t *out, int opcode,
scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1,
scc_x86_operand_value_t op2,
scc_pos_t pos) {
static inline void
scc_mir_x86_instr_3(scc_mir_x86_instr_t *out, scc_x86_iform_t opcode,
scc_x86_operand_value_t op0, scc_x86_operand_value_t op1,
scc_x86_operand_value_t op2, scc_pos_t pos) {
out->x86_instr.opcode = opcode;
out->x86_instr.num_operands = 3;
out->x86_instr.operands[0] = op0;
@@ -105,4 +101,48 @@ static inline void scc_mir_x86_instr_3(scc_mir_x86_instr_t *out, int opcode,
out->x86_instr.src_loc = pos;
}
static inline scc_x86_iform_t
scc_mir_x86_mov_reg_mem(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.kind == SCC_X86_OPR_REG && op1.kind == SCC_X86_OPR_MEM);
return op0.size == 1 ? SCC_X86_IFORM_MOV_GPR8_MEMB
: SCC_X86_IFORM_MOV_GPRV_MEMV;
}
static inline scc_x86_iform_t
scc_mir_x86_mov_mem_reg(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.kind == SCC_X86_OPR_MEM && op1.kind == SCC_X86_OPR_REG);
return op0.size == 1 ? SCC_X86_IFORM_MOV_MEMB_GPR8
: SCC_X86_IFORM_MOV_MEMV_GPRV;
}
static inline scc_x86_iform_t
scc_mir_x86_mov_reg_reg(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.kind == SCC_X86_OPR_REG && op1.kind == SCC_X86_OPR_REG);
return op0.size == 1 ? SCC_X86_IFORM_MOV_GPR8_GPR8_8A
: SCC_X86_IFORM_MOV_GPRV_GPRV_8B;
}
static inline scc_x86_iform_t
scc_mir_x86_mov_reg_imm(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.kind == SCC_X86_OPR_REG && op1.kind == SCC_X86_OPR_IMM);
return op0.size == 1 ? SCC_X86_IFORM_MOV_GPR8_IMMB_B0
: SCC_X86_IFORM_MOV_GPRV_IMMV;
}
void scc_x86_emit_move_to_vec(scc_mir_x86_instr_vec_t *vec,
scc_x86_operand_value_t dst,
scc_x86_operand_value_t src);
void scc_x86_emit_load_to_vec(scc_mir_x86_instr_vec_t *vec,
scc_x86_operand_value_t dst,
scc_x86_operand_value_t src_addr);
void scc_x86_emit_store_to_vec(scc_mir_x86_instr_vec_t *vec,
scc_x86_operand_value_t dst_addr,
scc_x86_operand_value_t src);
#endif /* __SCC_X86_MIR_H__ */