zzy/scc
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

feat(ast2ir): 实现C11类型提升系统并重构HIR基本块管理

Browse Source 
- 新增 scc_ast2ir_promote.c 实现整数提升(6.3.1.1)和寻常算术转换(6.3.1.8)
- 重构 HIR Builder: bblock → create_bblock + append_bblock，引入BBList链表管理
- AST2IR 全面集成类型提升：二元运算、赋值、函数调用参数、自增/自减操作符
- 变参函数支持：跳过 ... 假参数，实现默认参数提升(float→double等)
- 简化 HIR Dump 实现
- MIR: Win64 ABI改进、x86指令选择优化
- 新增 printf 测试用例
This commit is contained in:
zzy
2026-05-24 15:46:22 +08:00
parent ea553718f0
commit cec96333e7
27 changed files with 1223 additions and 740 deletions
Download Patch File Download Diff File Expand all files Collapse all files

98
libs/ir/mir/src/arch/scc_x86_mir.c
View File

@@ -1,5 +1,47 @@
#include <arch/scc_x86_mir.h>
static inline scc_x86_iform_t
scc_mir_x86_mov_reg_mem(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.kind == SCC_X86_OPR_REG && op1.kind == SCC_X86_OPR_MEM);
return op0.size == 1 ? SCC_X86_IFORM_MOV_GPR8_MEMB
: SCC_X86_IFORM_MOV_GPRV_MEMV;
}
static inline scc_x86_iform_t
scc_mir_x86_mov_reg_reg(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.kind == SCC_X86_OPR_REG && op1.kind == SCC_X86_OPR_REG);
return op0.size == 1 ? SCC_X86_IFORM_MOV_GPR8_GPR8_8A
: SCC_X86_IFORM_MOV_GPRV_GPRV_8B;
}
static inline scc_x86_iform_t
scc_mir_x86_mov_reg_imm(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.kind == SCC_X86_OPR_REG && op1.kind == SCC_X86_OPR_IMM);
return op0.size == 1 ? SCC_X86_IFORM_MOV_GPR8_IMMB_B0
: SCC_X86_IFORM_MOV_GPRV_IMMV;
}
static inline scc_x86_iform_t
scc_mir_x86_mov_mem_reg(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.kind == SCC_X86_OPR_MEM && op1.kind == SCC_X86_OPR_REG);
return op0.size == 1 ? SCC_X86_IFORM_MOV_MEMB_GPR8
: SCC_X86_IFORM_MOV_MEMV_GPRV;
}
static inline scc_x86_iform_t
scc_mir_x86_mov_mem_imm(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.kind == SCC_X86_OPR_MEM && op1.kind == SCC_X86_OPR_IMM);
return op0.size == 1 ? SCC_X86_IFORM_MOV_MEMB_IMMB
: SCC_X86_IFORM_MOV_MEMV_IMMZ;
}
void scc_x86_emit_move_to_vec(scc_mir_x86_instr_vec_t *vec,
scc_x86_operand_value_t dst,
scc_x86_operand_value_t src) {
@@ -7,21 +49,35 @@ void scc_x86_emit_move_to_vec(scc_mir_x86_instr_vec_t *vec,
LOG_WARN("Mismatched register sizes for move %d != %d", dst.size,
src.size);
}
Assert(dst.kind == SCC_X86_OPR_REG);
scc_mir_x86_instr_t ins;
if (src.kind == SCC_X86_OPR_REG) {
scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_reg_reg(dst, src), dst, src,
scc_pos_create());
} else if (src.kind == SCC_X86_OPR_IMM) {
scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_reg_imm(dst, src), dst, src,
scc_pos_create());
} else if (src.kind == SCC_X86_OPR_MEM ||
(src.kind == SCC_X86_OPR_RELOC &&
src.reloc.target == SCC_X86_RELOC_TARGET_SYMBOL)) {
scc_mir_x86_instr_2(&ins, SCC_X86_IFORM_LEA_GPRV_AGEN, dst, src,
scc_pos_create());
if (dst.kind == SCC_X86_OPR_REG) {
if (src.kind == SCC_X86_OPR_REG) {
scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_reg_reg(dst, src), dst,
src, scc_pos_create());
} else if (src.kind == SCC_X86_OPR_IMM) {
scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_reg_imm(dst, src), dst,
src, scc_pos_create());
} else if (src.kind == SCC_X86_OPR_MEM ||
(src.kind == SCC_X86_OPR_RELOC &&
src.reloc.target == SCC_X86_RELOC_TARGET_SYMBOL)) {
Assert(dst.size == 8);
scc_mir_x86_instr_2(&ins, SCC_X86_IFORM_LEA_GPRV_AGEN, dst, src,
scc_pos_create());
} else {
Panic("emit_move: unsupported src kind %d", src.kind);
}
} else if (dst.kind == SCC_X86_OPR_MEM) {
if (src.kind == SCC_X86_OPR_IMM) {
scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_mem_imm(dst, src), dst,
src, scc_pos_create());
} else if (src.kind == SCC_X86_OPR_REG) {
scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_mem_reg(dst, src), dst,
src, scc_pos_create());
} else {
Panic("emit_move: unsupported src kind %d", src.kind);
}
} else {
Panic("emit_move: unsupported src kind %d", src.kind);
Panic("emit_move: unsupported dst kind %d", dst.kind);
}
scc_vec_push(*vec, ins);
}
@@ -65,7 +121,6 @@ void scc_x86_emit_store_to_vec(scc_mir_x86_instr_vec_t *vec,
LOG_WARN("Mismatched sizes for store %d != %d", dst_addr.size,
src.size);
}
Assert(src.kind == SCC_X86_OPR_REG);
scc_x86_operand_value_t mem_op;
if (dst_addr.kind == SCC_X86_OPR_REG) {
mem_op = (scc_x86_operand_value_t){
@@ -83,10 +138,17 @@ void scc_x86_emit_store_to_vec(scc_mir_x86_instr_vec_t *vec,
} else if (dst_addr.kind == SCC_X86_OPR_MEM) {
mem_op = dst_addr;
} else {
Panic("emit_store: dst_addr must be REG or MEM");
Panic("emit_store: dst_addr kind not supported %d", dst_addr.kind);
}
scc_mir_x86_instr_t ins;
scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_mem_reg(mem_op, src), mem_op, src,
scc_pos_create());
if (src.kind == SCC_X86_OPR_REG) {
scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_mem_reg(mem_op, src), mem_op,
src, scc_pos_create());
} else if (src.kind == SCC_X86_OPR_IMM) {
scc_mir_x86_instr_2(&ins, scc_mir_x86_mov_mem_imm(mem_op, src), mem_op,
src, scc_pos_create());
} else {
Panic("unsupported src kind not supported %d", src.kind);
}
scc_vec_push(*vec, ins);
}
}