feat(mir): 实现x86-64架构寄存器分配和指令选择优化

- 修改x86_64_isel.h接口,将func_meta替换为func指针,并添加新的isel函数原型
- 添加x86_64_reg_alloc.h头文件,提供架构特定的寄存器分配操作填充函数
- 更新frame_layout.h定义frame_layout上下文结构
- 重构reg_alloc.h中的寄存器分配操作结构体,将ops从指针改为值类型,
  并将mark_reg_unused重命名为clean_mark_regs
- 扩展scc_mir.h中的函数元数据,添加vregs_count字段和虚拟寄存器管理函数
- 重新定义MIR pass阶段枚举,添加FRAME_LAYOUT和PROLOGUE_EPILOGUE阶段
- 添加win64目标相关头文件和实现,提供Windows x64 ABI降低和寄存器分配填充
- 更新虚拟寄存器表示格式从$到%,修复alloca指令处理
- 重构寄存器分配算法,改进虚拟寄存器到物理寄存器/栈槽的映射机制
- 完善MIR pass调度,支持多阶段处理流程
This commit is contained in:
zzy
2026-05-12 10:55:58 +08:00
parent 4f40f0d5e4
commit 68eac24152
17 changed files with 386 additions and 115 deletions

View File

@@ -4,6 +4,7 @@
#include <arch/x86_64_isel.h>
#include <core_pass/scc_abi_lowering.h>
#include <core_pass/scc_prolog_epilog.h>
#include <target/scc_win64.h>
static const int WIN64_DEFAULT_ALIGN = 8;
static const int WIN64_STACK_ALIGN = 16;
@@ -199,6 +200,44 @@ void scc_win_pc_x64_abi_lowering(scc_abi_lowering_t *abi_lowering) {
abi_lowering->lower_va_end = nullptr;
}
static const int reg_pool[] = {
SCC_X86_REG_R8, SCC_X86_REG_R9, SCC_X86_REG_R10, SCC_X86_REG_R11,
SCC_X86_REG_R12, SCC_X86_REG_R13, SCC_X86_REG_R14, SCC_X86_REG_R15};
static uint32_t reg_mask = 0; // 1 表示已占用
static int acquire_reg(void *ctx) {
for (int i = 0; i < SCC_ARRLEN(reg_pool); i++)
if (!(reg_mask & (1u << i))) {
reg_mask |= (1u << i);
return reg_pool[i];
}
UNREACHABLE(); // 可改为溢出逻辑
}
static void release_reg(void *ctx, int preg) {
for (int i = 0; i < SCC_ARRLEN(reg_pool); i++)
if (reg_pool[i] == preg) {
reg_mask &= ~(1u << i);
return;
}
}
static void mark_reg_used(void *ctx, int preg) {
for (int i = 0; i < SCC_ARRLEN(reg_pool); i++)
if (reg_pool[i] == preg) {
reg_mask |= (1u << i);
return;
}
}
static void clean_mark_regs(void *ctx) { reg_mask = 0; }
void scc_reg_alloc_fill_win_x64(scc_reg_alloc_op_t *ops) {
ops->acquire_reg = acquire_reg;
ops->release_reg = release_reg;
ops->mark_reg_used = mark_reg_used;
ops->clean_mark_regs = clean_mark_regs;
}
void scc_win_pc_x64_prolog_epilog(scc_prolog_epilog_t *prolog_epilog) {
prolog_epilog->prolog = prologue;
prolog_epilog->epilog = epilogue;