feat(mir): 添加寄存器分配 pass 支持

- 实现了核心寄存器分配接口 scc_reg_alloc.h
- 添加 x86_64 架构特定的寄存器分配实现
- 实现基础的虚拟寄存器到物理寄存器分配逻辑
- 支持栈槽分配和重载/存储指令生成

fix(argparse): 修复帮助信息打印中的枚举类型显示

- 将固定大小缓冲区改为动态字符串处理
- 正确显示枚举类型的选项值和可选值列表
- 使用 | 分隔符展示多个可选值

refactor(main): 调整编译流程中的 pass 阶段支持

- 更新配置文件中各编译阶段的名称定义
- 添加对寄存器分配、帧布局等中间表示 pass 的支持
- 重构主流程以支持不同 MIR 阶段的代码输出

libs/ir/mir/src/arch/x86_64_reg_alloc.c

@@ -0,0 +1,86 @@
+#include <arch/x86_64_isel.h>
+#include <core_pass/scc_reg_alloc.h>
+
+static void x86_emit_spill(scc_mir_instr_vec_t *ctx, int preg, int slot) {
+    scc_mir_instr_t ins = {
+        .opcode = SCC_X86_IFORM_MOV_MEMV_GPRV,
+        .num_operands = 2,
+        .operands = {{.kind = SCC_MIR_OP_MEM, .stack_slot = slot},
+                     {.kind = SCC_MIR_OP_PREG, .preg = preg}}};
+    scc_vec_push(*ctx, ins);
+}
+
+static void x86_emit_reload(scc_mir_instr_vec_t *ctx, int preg, int slot) {
+    scc_mir_instr_t ins = {
+        .opcode = SCC_X86_IFORM_MOV_GPRV_MEMV,
+        .num_operands = 2,
+        .operands = {{.kind = SCC_MIR_OP_PREG, .preg = preg},
+                     {.kind = SCC_MIR_OP_MEM, .stack_slot = slot}}};
+    scc_vec_push(*ctx, ins);
+}
+
+static void x86_emit_copy(scc_mir_instr_vec_t *ctx, int dst_preg, int src_preg,
+                          int size) {
+    scc_mir_instr_t ins = {
+        .opcode = SCC_X86_IFORM_MOV_GPRV_GPRV_89,
+        .num_operands = 2,
+        .operands = {{.kind = SCC_MIR_OP_PREG, .preg = dst_preg},
+                     {.kind = SCC_MIR_OP_PREG, .preg = src_preg}}};
+    scc_vec_push(*ctx, ins);
+}
+
+/* ---- 临时寄存器 ---- */
+static int x86_acquire_temp_reg(void *vctx) { return SCC_X86_REG_R11; }
+
+static void x86_release_temp_reg(void *vctx, int preg) { /* 简单模式无需操作 */
+}
+
+/* ---- 操作数读写属性 ---- */
+static scc_op_access_t x86_get_operand_access(void *vctx, int opcode,
+                                              int op_idx) {
+    switch (opcode) {
+    default:
+        return SCC_REG_ALLOC_OP_ACCESS_READWRITE; // 保守
+    }
+}
+
+/* ---- 隐式寄存器 ---- */
+static void x86_get_implicit_regs(void *vctx, int opcode, const int **uses,
+                                  const int **defs) {
+    static const int empty[] = {-1};
+    static const int rax[] = {SCC_X86_REG_RAX, -1};
+    static const int rdx[] = {SCC_X86_REG_RDX, -1};
+    static const int rax_rdx[] = {SCC_X86_REG_RAX, SCC_X86_REG_RDX, -1};
+    static const int cl[] = {SCC_X86_REG_CL, -1};
+
+    switch (opcode) {
+    case SCC_X86_IFORM_IDIV_GPRV:
+    case SCC_X86_IFORM_DIV_GPRV:
+        *uses = rax_rdx;
+        *defs = rax_rdx;
+        break;
+    case SCC_X86_IFORM_CQO:
+        *uses = rax;
+        *defs = rax_rdx;
+        break;
+    case SCC_X86_IFORM_SAR_GPRV_CL:
+        *uses = cl;
+        *defs = empty;
+        break;
+    default:
+        *uses = empty;
+        *defs = empty;
+        break;
+    }
+}
+
+/* 组装 hooks 表 */
+scc_reg_alloc_op_t x86_reg_alloc_hooks = {
+    .emit_spill = x86_emit_spill,
+    .emit_reload = x86_emit_reload,
+    .emit_copy = x86_emit_copy,
+    .acquire_reg = x86_acquire_temp_reg,
+    .release_reg = x86_release_temp_reg,
+    .get_operand_access = x86_get_operand_access,
+    .get_implicit_regs = x86_get_implicit_regs,
+};