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refactor(ast2ir): 重构ABI类型系统并修复union结构问题

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- 将scc_ast_def.h中的attr_of从union改为struct以修复结构定义问题
- 添加type_abi依赖到ast2ir模块的cbuild.toml配置文件中
- 重命名scc_ast2ir.h中的abi字段为type_abi，并更新相关初始化函数签名
- 移除废弃的scc_abi_type.h和相关平台ABI头文件
- 添加辅助函数is_variadic_marker和fixed_param_count用于处理可变参数
- 添加数组和聚合类型初始化的辅助函数
This commit is contained in:
zzy
2026-06-01 12:14:13 +08:00
parent 8b817da3b6
commit 31d7e91ef1
45 changed files with 1918 additions and 1551 deletions
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63
libs/ir/mir/src/arch/scc_x86_mir.c
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@@ -3,63 +3,64 @@
static inline scc_x86_iform_t
scc_mir_x86_mov_reg_mem(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.size_bits == op1.size_bits);
Assert(op0.kind == SCC_X86_OPR_REG && op1.kind == SCC_X86_OPR_MEM);
return op0.size == 1 ? SCC_X86_IFORM_MOV_GPR8_MEMB
: SCC_X86_IFORM_MOV_GPRV_MEMV;
return op0.size_bits == 8 ? SCC_X86_IFORM_MOV_GPR8_MEMB
: SCC_X86_IFORM_MOV_GPRV_MEMV;
}
static inline scc_x86_iform_t
scc_mir_x86_mov_reg_reg(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.size_bits == op1.size_bits);
Assert(op0.kind == SCC_X86_OPR_REG && op1.kind == SCC_X86_OPR_REG);
return op0.size == 1 ? SCC_X86_IFORM_MOV_GPR8_GPR8_8A
: SCC_X86_IFORM_MOV_GPRV_GPRV_8B;
return op0.size_bits == 8 ? SCC_X86_IFORM_MOV_GPR8_GPR8_8A
: SCC_X86_IFORM_MOV_GPRV_GPRV_8B;
}
static inline scc_x86_iform_t
scc_mir_x86_mov_reg_imm(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.size_bits == op1.size_bits);
Assert(op0.kind == SCC_X86_OPR_REG && op1.kind == SCC_X86_OPR_IMM);
return op0.size == 1 ? SCC_X86_IFORM_MOV_GPR8_IMMB_B0
: SCC_X86_IFORM_MOV_GPRV_IMMV;
return op0.size_bits == 8 ? SCC_X86_IFORM_MOV_GPR8_IMMB_B0
: SCC_X86_IFORM_MOV_GPRV_IMMV;
}
static inline scc_x86_iform_t
scc_mir_x86_mov_mem_reg(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.size_bits == op1.size_bits);
Assert(op0.kind == SCC_X86_OPR_MEM && op1.kind == SCC_X86_OPR_REG);
return op0.size == 1 ? SCC_X86_IFORM_MOV_MEMB_GPR8
: SCC_X86_IFORM_MOV_MEMV_GPRV;
return op0.size_bits == 8 ? SCC_X86_IFORM_MOV_MEMB_GPR8
: SCC_X86_IFORM_MOV_MEMV_GPRV;
}
static inline scc_x86_iform_t
scc_mir_x86_mov_mem_imm(scc_x86_operand_value_t op0,
scc_x86_operand_value_t op1) {
Assert(op0.size == op1.size);
Assert(op0.size_bits == op1.size_bits);
Assert(op0.kind == SCC_X86_OPR_MEM && op1.kind == SCC_X86_OPR_IMM);
return op0.size == 1 ? SCC_X86_IFORM_MOV_MEMB_IMMB
: SCC_X86_IFORM_MOV_MEMV_IMMZ;
return op0.size_bits == 8 ? SCC_X86_IFORM_MOV_MEMB_IMMB
: SCC_X86_IFORM_MOV_MEMV_IMMZ;
}
static inline u8 get_op_size(scc_x86_operand_value_t op, cbool get_value) {
static inline u8 get_op_size_bits(scc_x86_operand_value_t op, cbool get_value) {
if (get_value) {
return op.size;
return op.size_bits;
}
if (op.kind == SCC_X86_OPR_MEM) {
return 8;
return 64;
}
if (op.kind == SCC_X86_OPR_RELOC && op.reloc.kind == SCC_X86_OPR_MEM) {
return 8;
return 64;
}
return op.size;
return op.size_bits;
}
void scc_x86_emit_move_to_vec(scc_mir_x86_instr_vec_t *vec,
scc_x86_operand_value_t dst,
scc_x86_operand_value_t src) {
u8 dst_size = get_op_size(dst, false);
u8 src_size = get_op_size(src, false);
u8 dst_size = get_op_size_bits(dst, false);
u8 src_size = get_op_size_bits(src, false);
if (dst_size != src_size) {
LOG_FATAL("Mismatched register sizes for move %d != %d", dst_size,
src_size);
@@ -75,7 +76,7 @@ void scc_x86_emit_move_to_vec(scc_mir_x86_instr_vec_t *vec,
} else if (src.kind == SCC_X86_OPR_MEM ||
(src.kind == SCC_X86_OPR_RELOC &&
src.reloc.target == SCC_X86_RELOC_TARGET_SYMBOL)) {
Assert(dst_size == 8);
Assert(dst_size == 64);
scc_mir_x86_instr_2(&ins, SCC_X86_IFORM_LEA_GPRV_AGEN, dst, src,
scc_pos_create());
} else {
@@ -100,8 +101,8 @@ void scc_x86_emit_move_to_vec(scc_mir_x86_instr_vec_t *vec,
void scc_x86_emit_load_to_vec(scc_mir_x86_instr_vec_t *vec,
scc_x86_operand_value_t dst,
scc_x86_operand_value_t src_addr) {
u8 dst_size = get_op_size(dst, false);
u8 src_addr_size = get_op_size(src_addr, true);
u8 dst_size = get_op_size_bits(dst, false);
u8 src_addr_size = get_op_size_bits(src_addr, true);
if (dst_size != src_addr_size) {
LOG_FATAL("Mismatched sizes for load %d != %d", dst_size,
src_addr_size);
@@ -117,9 +118,9 @@ void scc_x86_emit_load_to_vec(scc_mir_x86_instr_vec_t *vec,
.index = SCC_X86_REG_INVALID,
.scale = 1,
.disp.displacement = 0,
.disp.displacement_bits = src_addr_size * 8,
.disp.displacement_bits = src_addr_size,
},
.size = src_addr_size,
.size_bits = src_addr_size,
};
} else if (src_addr.kind == SCC_X86_OPR_MEM) {
mem_op = src_addr;
@@ -135,8 +136,8 @@ void scc_x86_emit_load_to_vec(scc_mir_x86_instr_vec_t *vec,
void scc_x86_emit_store_to_vec(scc_mir_x86_instr_vec_t *vec,
scc_x86_operand_value_t dst_addr,
scc_x86_operand_value_t src) {
u8 dst_addr_size = get_op_size(dst_addr, true);
u8 src_size = get_op_size(src, false);
u8 dst_addr_size = get_op_size_bits(dst_addr, true);
u8 src_size = get_op_size_bits(src, false);
if (dst_addr_size != src_size) {
LOG_FATAL("Mismatched sizes for store %d != %d", dst_addr_size,
src_size);
@@ -151,9 +152,9 @@ void scc_x86_emit_store_to_vec(scc_mir_x86_instr_vec_t *vec,
.index = SCC_X86_REG_INVALID,
.scale = 1,
.disp.displacement = 0,
.disp.displacement_bits = dst_addr_size * 8,
.disp.displacement_bits = dst_addr_size,
},
.size = dst_addr_size,
.size_bits = dst_addr_size,
};
} else if (dst_addr.kind == SCC_X86_OPR_MEM) {
mem_op = dst_addr;