feat(backend/riscv32): 实现基础的编译器功能

- 完成 RV32IMA 指令集的代码生成
- 添加整数运算、分支、调用等基本指令支持
- 实现从 IR 到机器码的转换
- 添加简单的测试用例和测试框架

ccompiler/backend/riscv32/rv32gen.h

@@ -211,7 +211,7 @@ typedef enum {
 #define SLTZ(rd, rs) SLT(rd, rs, REG_X0) // 小于0则置位
 
 // sgtz rd, rs (Set if > zero)
-#define SG TZ(rd, rs) SLT(rd, REG_X0, rs) // 大于0则置位
+#define SGTZ(rd, rs) SLT(rd, REG_X0, rs) // 大于0则置位
 
 // beqz rs, offset (Branch if = zero)
 #define BEQZ(rs, offset) BEQ(rs, REG_X0, offset) // 为0则转移
@@ -291,13 +291,16 @@ typedef enum {
 #define LI(rd, num) \
     LUI(rd, num), \
     ADDI(rd, rd, num)
-
 #define MV(rd, rs)  ADDI(rd, rs, 0)
 #define NOT(rd, rs) XORI(rd, rs, -1)
-#define CALL(offset) \
-    AUIPC(REG_X1, offset), \
-    JALR(REG_X1, REG_X1, offset)
+#define SEQZ(rd, rs) SLTIU(rd, rs, 1)
 
+#define SGT(rd, rs1, rs2) SLT(rd, rs2, rs1)
+
+// TODO call have error when outof jalr
+#define CALL(offset) \
+    AUIPC(REG_X1, REG_X0), \
+    JALR(REG_X1, REG_X1, offset)
 #define CALL_ABS(addr) \
     AUIPC(REG_X0, addr), \
     JALR(REG_X1, REG_X0, addr)