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> compile NEMU

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221220000 张三
Linux zzy 5.15.146.1-microsoft-standard-WSL2 #1 SMP Thu Jan 11 04:09:03 UTC 2024 x86_64 x86_64 x86_64 GNU/Linux
 19:47:12 up 4 days, 14:52,  1 user,  load average: 1.21, 0.49, 0.38
This commit is contained in:
tracer-ics2023
2024-09-21 19:47:13 +08:00
committed by zzy
parent dfc38f6525
commit 5024b50130
3 changed files with 24 additions and 1 deletions
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1
nemu/src/isa/riscv32/include/isa-def.h
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@ -20,6 +20,7 @@
typedef struct {
word_t gpr[MUXDEF(CONFIG_RVE, 16, 32)];
word_t cpr[0x1000]; // Control and Status Register
vaddr_t pc;
} MUXDEF(CONFIG_RV64, riscv64_CPU_state, riscv32_CPU_state);

13
nemu/src/isa/riscv32/inst.c
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@ -21,6 +21,7 @@
#include <limits.h>
#define R(i) gpr(i)
#define C(i) cpr(i)
#define Mr vaddr_read
#define Mw vaddr_write
@ -116,7 +117,7 @@ static int decode_exec(Decode *s) {
INSTPAT("0000000 ????? ????? 110 ????? 01100 11", or , R, R(rd) = src1 | src2);
INSTPAT("0000000 ????? ????? 111 ????? 01100 11", and , R, R(rd) = src1 & src2);
// INSTPAT("0000000 00000 00000 000 00000 11100 11", ecall , N, );
INSTPAT("0000000 00000 00000 000 00000 11100 11", ecall , N, C(MEPC) = s->pc, C(MSTATUS) = 0x1800, s->dnpc = C(MTVEC));
INSTPAT("0000000 00001 00000 000 00000 11100 11", ebreak , N, NEMUTRAP(s->pc, R(10))); // R(10) is $a0
INSTPAT("0000001 ????? ????? 000 ????? 01100 11", mul , R, R(rd) = (sword_t)src1 * (sword_t)src2);
@ -128,6 +129,16 @@ static int decode_exec(Decode *s) {
INSTPAT("0000001 ????? ????? 110 ????? 01100 11", rem , R, R(rd) = (src1 == INT_MIN && src2 == -1) ? 0 : (src2 ? (sword_t) src1 % (sword_t) src2 : src1));
INSTPAT("0000001 ????? ????? 111 ????? 01100 11", remu , R, R(rd) = src2 ? (word_t)src1 %(word_t) src2 : src1);
INSTPAT("??????? ????? ????? 001 ????? 11100 11", csrrw , I, R(rd) = C(imm), C(imm) = src1);
// INSTPAT("??????? ????? ????? 010 ????? 11100 11", csrrs , I, );
// INSTPAT("??????? ????? ????? 011 ????? 11100 11", csrrc , I, );
// INSTPAT("??????? ????? ????? 101 ????? 11100 11", csrrwi , I, );
// INSTPAT("??????? ????? ????? 110 ????? 11100 11", csrrsi , I, );
// INSTPAT("??????? ????? ????? 111 ????? 11100 11", csrrci , I, );
// INSTPAT("0001000 00010 00000 000 00000 11100 11", sret , R, );
INSTPAT("0011000 00010 00000 000 00000 11100 11", mret , R, s->dnpc = C(MEPC));
INSTPAT("??????? ????? ????? ??? ????? ????? ??", inv , N, INV(s->pc));
INSTPAT_END();

11
nemu/src/isa/riscv32/local-include/reg.h
View File

@ -25,6 +25,17 @@ static inline int check_reg_idx(int idx) {
#define gpr(idx) (cpu.gpr[check_reg_idx(idx)])
#define MSTATUS 0x300 // Machine status register.
#define MTVEC 0x305 // Machine trap-handler base address.
#define MEPC 0x341 // Machine exception program counter.
#define MCAUSE 0x342 // Machine trap cause.
static inline int check_cpr_idx(int idx) {
IFDEF(CONFIG_RT_CHECK, assert(idx == MSTATUS || idx == MEPC || idx == MCAUSE));
return idx;
}
#define cpr(idx) (cpu.cpr[check_cpr_idx(idx)])
static inline const char* reg_name(int idx) {
extern const char* regs[];
return regs[check_reg_idx(idx)];